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기능 Digital-to-Analog Converter
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AD9154 데이터시트, 핀배열, 회로
Data Sheet
Quad, 16-Bit, 2.4 GSPS, TxDAC+®
Digital-to-Analog Converter
AD9154
FEATURES
Supports input data rates up to 1 GSPS
Proprietary, low spurious and distortion design
Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at
180 MHz IF
Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at
180 MHz IF
SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone
Flexible 8-lane JESD204B interface
Multiple chip synchronization
Fixed latency
Data generator latency compensation
Input signal power detection
High performance, low noise phase-locked loop (PLL) clock
multiplier
Digital inverse sinc filter
Digital quadrature modulation using a numerically
controlled oscillator (NCO)
Nyquist band selection—mix mode
Selectable 1×, 2×, 4×, and 8× interpolation filters
Low power: 2.11 W at 1.6 GSPS, full operating conditions
88-lead, exposed pad LFCSP
APPLICATIONS
Wireless communications
Multicarrier LTE and GSM base stations
Wideband repeaters
Software defined radios
Wideband communications
Point to point microwave radio
Transmit diversity, multiple input/multiple output (MIMO)
Instrumentation
Automated test equipment
GENERAL DESCRIPTION
The AD9154 is a quad, 16-bit, high dynamic range digital-to-
analog converter (DAC) that provides a maximum sample rate
of 2.4 GSPS, permitting multicarrier generation up to the Nyquist
frequency in baseband mode. The AD9154 includes features
optimized for direct conversion transmit applications, including
complex digital modulation, input signal power detection, and
gain, phase, and offset compensation. The DAC outputs are
optimized to interface seamlessly with the ADRF6720-27 radio
frequency quadrature modulator (AQM) from Analog Devices,
Inc. In mix mode, the AD9154 DAC can reconstruct carriers in
the second and third Nyquist zones. A serial port interface (SPI)
provides the programming/readback of internal parameters.
The full-scale output current can be programmed over a range
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
QUAD MOD
ADRF6720-27
DAC
RF
OUTPUT
0°/90° PHASE
SHIFTER
LPF
DAC
JESD204B
SYNCOUTx±
SYSREF
LO_IN
MOD_SPI
QUAD MOD
ADRF6720-27
QUAD DAC
DAC
RF
OUTPUT 1
0°/90° PHASE
SHIFTER
LPF
LO_IN
DAC
AD9154
MOD_SPI
DAC DAC
CLOCK SPI
Figure 1.
JESD204B
SYNCOUTx±
of 4 mA to 20 mA. The AD9154 is available in two different
88-lead LFCSP packages.
PRODUCT HIGHLIGHTS
1. Ultrawide signal bandwidth enables emerging wideband
and multiband wireless applications.
2. Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
3. JESD204B Subclass 1 support simplifies multichip
synchronization.
4. Small package size with a 12 mm × 12 mm footprint.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD9154 pdf, 반도체, 판매, 대치품
AD9154
Data Sheet
DETAILED FUNCTIONAL BLOCK DIAGRAM
SERDES
PLL
DACCLK
HB1
HB2
HB3
COMPLEX
MODULATION
VTT
SERDIN7±
MODE CONTROL
HB1 HB2
HB3
NCO
fDAC
÷4, ÷8
Q GAIN
Q OFFSET
PHASE
I GAIN ADJUST I OFFSET
FSC
DACCLK
FSC
OUT3+
OUT3–
OUT2+
OUT2–
SERDIN0±
PDP OUT0
PDP OUT1
SYNCOUT0+
SYNCOUT0–
SYNCOUT1+
SYNCOUT1–
HB1 HB2
HB3
MODE CONTROL
HB1 HB2
HB3
COMPLEX
MODULATION
NCO
fDAC
÷4, ÷8
Q GAIN
Q OFFSET
PHASE
I GAIN ADJUST I OFFSET
FSC
DACCLK
FSC
SYNCHRONIZATION
LOGIC
CONFIG
REGISTERS
CLOCK DISTRIBUTION
AND
CONTROL LOGIC
SERIAL
I/O PORT
POWER-ON
RESET
DACCLK
PLL_LOCK
DAC
ALIGN
DETECT
DAC PLL
REF
AND
BIAS
SYSREF
RCVR
CLK
RCVR
OUT1+
OUT1–
OUT0+
OUT0–
I120
SYSREF+
SYSREF–
CLK+
CLK–
Figure 2. Detailed Functional Block Diagram
Rev. B | Page 4 of 124

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AD9154 전자부품, 판매, 대치품
Data Sheet
AD9154
Parameter
CS to SCLK
Setup Time
Hold Time
Symbol Test Conditions/Comments
tSCS
tHCSCS
1 See Table 3 for detailed specifications for DAC update rate conditions.
2 Maximum speed for 1× interpolation is limited by the JESD204B interface. See Table 4 for details.
3 Maximum speed for 2× interpolation is limited by the JESD204B interface. See Table 4 for details.
4 See Table 4 for detailed specifications for JESD204B speed conditions.
5 CLK+/CLK− serve as a reference oscillator input for the on-chip PLL clock multiplier when in use.
6 K, F, and S are JESD204B transport layer parameters. See Table 42 for the full definitions.
7 See Table 5 for detailed specifications for SYSREF to DAC clock timing conditions.
Min
5
2
Typ Max
Unit
ns
ns
MAXIMUM DAC UPDATE RATE SPEED SPECIFICATIONS BY SUPPLY
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V,
VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter
MAXIMUM DAC UPDATE RATE
Test Conditions/Comments
Min Typ Max Unit
DVDD12, CVDD12, PVDD12 = 1.2 V ± 5%
1.93
GSPS
DVDD12, CVDD12, PVDD12 = 1.2 V ± 2%
2.07
GSPS
DVDD12, CVDD12, PVDD12 = 1.3 V ± 2%
2.4
GSPS
JESD204B SERIAL INTERFACE SPEED SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 4.
Parameter
CLOCK AND DATA RECOVERY
(CDR) HALF RATE MODE
CDR FULL RATE MODE
CDR OVERSAMPLING MODE
Test Conditions/Comments
SVDD12 = 1.2 V ± 5%
SVDD12 = 1.2 V ±2%
SVDD12 = 1.3 V ± 2%
SVDD12 = 1.2 V ± 5%
SVDD12 = 1.2 V ±2%
SVDD12 = 1.3 V ± 2%
SVDD12 = 1.2 V ± 5%
SVDD12 = 1.2 V ±2%
SVDD12 = 1.3 V ± 2%
Min Typ Max Unit
5.74 9.04 Gbps
5.74 9.65 Gbps
5.74
10.96
Gbps
2.87 4.79 Gbps
2.87 4.93 Gbps
2.87 5.73 Gbps
1.44 2.39 Gbps
1.44 2.50 Gbps
1.44 2.93 Gbps
Rev. B | Page 7 of 124

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