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ADF5355 데이터시트 PDF




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부품번호 ADF5355 기능
기능 Microwave Wideband Synthesizer
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ADF5355 데이터시트, 핀배열, 회로
Data Sheet
Microwave Wideband Synthesizer
with Integrated VCO
ADF5355
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 54 MHz to 13,600 MHz
Fractional-N synthesizer and integer-N synthesizer
High resolution 38-bit modulus
Phase frequency detector (PFD) operation to 125 MHz
Reference frequency operation to 600 MHz
Maintains frequency lock over −40°C to +85°C
Low phase noise, voltage controlled oscillator (VCO)
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Analog and digital power supplies: 3.3 V
Charge pump and VCO power supplies: 5 V, typical
Logic compatibility: 1.8 V
Programmable dual modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
Analog and digital lock detect
Supported in the ADIsimPLL design tool
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA,
WiMAX, GSM, PCS, DCS, DECT)
Point to point/point to multipoint microwave links
Satellites/VSATs
Test equipment/instrumentation
Clock generation
The ADF5355 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
when used with an external loop filter and an external reference
frequency. The wideband microwave VCO design permits
frequency operation from 6.8 GHz to 13.6 GHz at one radio
frequency (RF) output. A series of frequency dividers at another
frequency output permits operation from 54 MHz to 6800 MHz.
The ADF5355 has an integrated VCO with a fundamental
output frequency ranging from 3400 MHz to 6800 MHz. In
addition, the VCO frequency is connected to divide by 1, 2, 4, 8,
16, 32, or 64 circuits that allow the user to generate RF output
frequencies as low as 54 MHz. For applications that require
isolation, the RF output stage can be muted. The mute function
is both pin and software controllable.
Control of all on-chip registers is through a simple 3-wire interface.
The ADF5355 operates with analog and digital power supplies
ranging from 3.15 V to 3.45 V, with charge pump and VCO
supplies from 4.75 V to 5.25 V. The ADF5355 also contains
hardware and software power-down modes.
CE AVDD
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP RSET VVCO
VRF
REFINA
REFIN B
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
INTEGER FRACTION MODULUS
REG
REG
REG
THIRD-ORDER
FRACTIONAL INTERPOLATOR
N COUNTER
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
VCO
CORE
×2
÷ 1/2/4/8/
16/32/64
MUXOUT
CREG1
CREG2
CPOUT
OUTPUT
STAGE
OUTPUT
STAGE
VTUNE
VREF
VBIAS
VREGVCO
RFOUTB
PDBRF
RFOUTA+
RFOUTA–
MULTIPLEXER
ADF5355
AGND
CPGND
AGNDRF
Figure 1.
SDGND AGNDVCO
Rev. A
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADF5355 pdf, 반도체, 판매, 대치품
ADF5355
Data Sheet
SPECIFICATIONS
AVDD = DVDD = VRF = 3.3 V ± 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred
to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
REFINA/REFINB CHARACTERISTICS
Input Frequency
Single-Ended Mode
Differential Mode
Input Sensitivity
Single-Ended Mode
Differential Mode
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
Phase Detector Frequency
CHARGE PUMP (CP)
Charge Pump Current, Sink/Source
High Value
Low Value
RSET Range
Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
LOGIC OUTPUTS
Output High Voltage
Output High Current
Output Low Voltage
POWER SUPPLIES
Analog Power
Digital Power and RF Supply Voltage
Charge Pump and VCO Supply Voltage
Charge Pump Supply Power Current
DIDD + AIDD3
Output Dividers
Supply Current
Symbol Min
Typ Max
10 250
10 600
0.4 AVDD
0.4 1.8
6.9
1.4
±60
±250
125
ICP
4.8
0.3
5.1
3
3
1.5
VINH
VINL
IINH/IINL
CIN
1.5
0.6
±1
3.0
VOH DVDD
0.4
1.5 1.8
IOH 500
VOL 0.4
AVDD
DVDD, VRF
VP, VVCO
IP
3.15
4.75
IVCO
AVDD
5.0
8
62
6 to
36
70
3.45
5.25
9
69
85
Unit
MHz
MHz
V p-p
V p-p
pF
pF
µA
µA
MHz
mA
mA
%
%
%
V
V
µA
pF
V
V
µA
V
V
V
mA
mA
mA
Test Conditions/Comments
For f < 10 MHz, ensure slew rate >
21 V/µs
REFINA biased at AVDD/2;
ac coupling ensures AVDD/2 bias
LVDS and LVPECL compatible,
REFINA/REFINB biased at 2.1 V;
ac coupling ensures 2.1 V bias
Single-ended reference programmed
Differential reference programmed
RSET = 5.1 kΩ
Fixed
0.5 V ≤ VCP1 ≤ VP − 0.5 V
0.5 V ≤ VCP1 ≤ VP − 0.5 V
VCP1 = 2.5 V
1.8 V output selected
IOL2 = 500 µA
See Table 6
Voltages must equal AVDD
VP must equal VVCO
Each output divide by 2 consumes
6 mA
Rev. A | Page 4 of 38

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ADF5355 전자부품, 판매, 대치품
Data Sheet
ADF5355
TIMING CHARACTERISTICS
AVDD = DVDD =VRF = 3.3 V ± 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred
to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Write Timing
Parameter
Limit
t1 20
t2 10
t3 10
t4 25
t5 25
t6 10
t7 20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Write Timing Diagram
CLK
DATA
DB31 (MSB)
LE
t1
t4 t5
t2 t3
DB30
DB3
(CONTROL BIT C4)
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
Figure 2. Write Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. A | Page 7 of 38

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ADF5355

Microwave Wideband Synthesizer

Analog Devices
Analog Devices

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