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ISL24201 데이터시트 PDF




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부품번호 ISL24201 기능
기능 Programmable Vcom Calibrator
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ISL24201 데이터시트, 핀배열, 회로
Programmable VCOM Calibrator with EEPROM
ISL24201
Features
The ISL24201 provides an 8-bit programmable current sink that
is used in conjunction with an external voltage divider and buffer
amplifier to generate a voltage source that is positioned between
the analog supply voltage and ground. The current sink’s
resolution is controlled by an external resistor, RSET, and the
span of the VCOM voltage is controlled by the voltage divider
resistor ratio and the source impedance of R1 and R2. This
device has an 8-bit data register and 8-bit EEPROM for storing a
volatile and a permanent value for its output. The ISL24201 has
an I2C bus interface that is used to read and write to its registers
and EEPROM. At power-up the EEPROM value is transferred to
the data register and output.
The ISL24201 is available in an 8 Ld 3mm x 3mm TDFN
package. This package has a maximum height of 0.8mm for very
low profile designs. The ambient operating temperature range is
-40°C to +85°C.
• 8-bit, 256-Step, Adjustable Sink Current Output
• 4.5V to 18V Analog Supply Voltage Operating Range
• 2.25V to 3.6V Logic Supply Voltage Operating Range
• 400kHz, I2C Interface
• On-Chip 8-Bit EEPROM
• Output Guaranteed Monotonic Over-Temperature
• Pb-free (RoHS-compliant)
Applications
• LCD Panel VCOM Generator
• Electrophoretic Display VCOM Generator
• Resistive Sensor Driver
• Low Power Current Loop
Related Literature
• See AN1621 for ISL24201 Evaluation Board Application Note
“ISL24201IRTZ-EVALZ Evaluation Board User Guide”
Typical Application
3.3V
VDD
AVDD
MICRO-
CONTROLLER
I2C
PORT
I/O PIN
52
6
SDA
7
SCL
3
WP
ISL24201
1
OUT
8
SET
4
R1
R2
RSET
EL5411T
LCD PANEL
VCOM
FIGURE 1. APPLICATION SHOWING ISL24201 WITH A BUFFER AMPLIFIER
December 9, 2010
FN7586.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2010. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.




ISL24201 pdf, 반도체, 판매, 대치품
ISL24201
Absolute Maximum Ratings
Supply Voltage
AVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
Input Voltage with respect to Ground
SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
SCL, SDA and WP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDD+0.3V
Output Voltage with respect to Ground
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD
Continuous Output Current
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . .1.5kV
Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld TDFN Package (Notes 4, 5). . . . . . . . .
53
11
Moisture Sensitivity (see Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Range
AVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5); unless otherwise
specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
MAX
TYP (Note 6) UNITS
DC CHARACTERISTICS
VDD
AVDD
AVDD
VDD Supply Range - Operating
AVDD Supply Range Supporting EEPROM Programming
AVDD Supply Range for Wide-Supply Operation
(not supporting EEPROM Programming)
2.25
10.8
4.5
3.6 V
19 V
19 V
IDD VDD Supply Current
IAVDD AVDD Supply Current
OUT CHARACTERISTICS
WP = SCL = SDA = VDD
WP = SCL = SDA = VDD
37 65
24 38
µA
µA
SETZSE
SETFSE
VOUT
SETVD
IOUT
INL
SET Zero-Scale Error
SET Full-Scale Error
OUT Voltage Range
SET Voltage Drift
Maximum OUT Sink Current
Integral Non-Linearity
IOUT < 0.5mA
VSET + 0.4
7
4
±3
±8
AVDD
±2
LSB
LSB
V
μV/°C
mA
LSB
DNL Differential Non-Linearity
I2C INPUTS AND OUTPUT
I2CVIH
I2CVIL
I2CH
SDA, SCL Logic 1 Input Voltage
SDA, SCL Logic 0 Input Voltage
SDA, SCL Hysteresis
IL Input Leakage Current of SDA, SCL
VOLS SDA Output Logic Low
VIH WP Input Logic High
VIL WP Input Logic Low
VWPH WP Input Hysteresis
ILWPN WP Input Leakage Current
I = -3mA
1.44
0.7VDD
-0.20
±1
0.55
260
±1
0.4
0.3VDD
260
-0.5 -1
LSB
V
V
mV
µA
V
V
V
mV
µA
4 FN7586.1
December 9, 2010

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ISL24201 전자부품, 판매, 대치품
ISL24201
The maximum voltage on the SET pin is AVDD/20 and is added to
the minimum voltage difference between the VOUT and SET pins to
calculate the minimum VOUT voltage, as shown in Equation 5.
VOUT(MIN) ≥ A----2V----D0---D-- + MinimumSaturationVoltage
(EQ. 5)
Output Voltage
The output voltage, VOUT, of the OUT pin can be calculated from
Equation 6:
VOUT
=
AVD
D
--R----1-R--+--2--R-----2--⎠⎟⎞
⎜⎛1
R-----e---g----i--s---t---e-2--r-5--V--6-a----l--u----e----+-----1--
2----0---R-R---1-S---E----T-⎠⎟⎞
(EQ. 6)
While Equation 6 can be used to calculate the output voltage, it
does not help select the values of R1, R2 and RSET to obtain a
specific range of VCOM voltages.
Output Voltage Span Calculation
The span of the output voltage is typically centered around the
nominal VCOM voltage value, which is typically near half of the
AVDD voltage. The high VCOM voltage occurs with the register
value of zero, while the low VCOM voltage occurs with the register
value of 255. Figure 7 shows the definition of several terms used
later in the text.
A VDD
HIGH VCOM VOLTAGE
NOMINAL VCOM VOLTAGE
SPAN
LOW VCOM VOLTAGE
GND
FIGURE 7. VOLTAGE LEVELS FOR VCOM
There are three variables that control the VCOM calibrator’s
operating point; the span of the VCOM voltage, the maximum
current sink and the source impedance of the resistive divider.
Figure 8 shows a range of operating points for these three variables
and a quick way to estimate a specific operating point. The X-axis is
the span of the VCOM voltage (High VCOM Voltage - Low VCOM
Voltage), and the Y-axis is the maximum sink current set by RSET.
The individual plots of each RTH show the VCOM span plotted against
the maximum OUT sink current given that value of source
impedance of the voltage divider. RTH is the Thevenin equivalent
resistance of the voltage divider R1 and R2, which is the resistance
of the parallel combination of R1 and R2, as shown in Equation 7.
RTH = R---R--1---1-+--R---R-2---2--
(EQ. 7)
The span of the VCOM voltage is shown by Equation 8.
VCOMSPAN = ISET(RTH)
(EQ. 8)
0.6
0.5
0.4
0.3
0.2
= 25kΩ
R TH
0.1 RTH = 50kΩ
RTH = 100kΩ
0
0123456
VCOM SPAN (V)
FIGURE 8. GRAPH of VCOM SPAN vs MAXIMUM OUTCURRENT
AND RTH
To make a final selection of the resistor values for R1 and R2, The
supply voltage AVDD and the value of RSET are specified. The
calculations for R1 and R2 are shown in Equations 9 and 10:
R1 = 4---A-0---V-R--D--S--D-E----T+---(--SS----PP----AA----NN-----)
(EQ. 9)
R2 = -4--A-0---V-R--D--S--D--E---T–---(--SS----PP----AA----NN-----)
(EQ. 10)
The R1 and R2 calculations are based on the span of the VCOM
voltage being centered at half the AVDD voltage.
As an example, AVDD = 15V, the maximum value for ISET is
selected to be 100µA and the required span is 2V. Using Figure 8
as a guide, the VCOM maximum is equal to 8.5V and the VCOM
minimum is equal to 6.5V. Rearranging equation and calculation
the value of RSET:
RSET = 2----0----I--O--A--U--V-T--D-(---MD-----A----X----) = 2----0----(--0----.-0-1---0-5--0----1---0----0----) = 7500Ω
(EQ. 11)
Calculating the value of R1 is shown in Equation 12.
R1 = 4----0----(--17---5-5---0-+---0--2--)--(---2----) = 39.29kΩ
(EQ. 12)
Calculating the value of R2 is shown in Equation 13.
R2 = 4----0----(--17---5-5---0-–---0--2--)--(---2----) = 46.15kΩ
(EQ. 13)
7 FN7586.1
December 9, 2010

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