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ISL24211 데이터시트 PDF




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부품번호 ISL24211 기능
기능 Programmable Vcom Calibrator
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ISL24211 데이터시트, 핀배열, 회로
Programmable VCOM Calibrator with EEPROM and
Output Buffer
ISL24211
The ISL24211 is an 8-bit programmable current sink that can be
used in conjunction with an external voltage divider to generate a
voltage source (VCOM) positioned between the analog supply
voltage and ground. The current sink’s full-scale range is
controlled by an external resistor, RSET. With the appropriate
choice of external resistors R1 and R2, the VCOM voltage range
can be controlled between any arbitrary voltage range. The
ISL24211 has an 8-bit data register and 8-bit EEPROM for storing
both a volatile and a permanent value for its output, with an I2C
interface to read and write to the register and EEPROM. After the
part is programmed, the I2C interface is no longer needed; on
power-up the EEPROM contents are automatically transferred to
the data register, and the pre-programmed output voltage
appears on the VCOM_OUT pin.
The ISL24211 also features an integrated, wide-bandwidth, high
output drive buffer amplifier that can directly drive the VCOM
input of an LCD panel.
The ISL24211 is available in an 10 Ld 3mm x 3mm TDFN
package. This package has a maximum height of 0.8mm for very
low profile designs. The ambient operating temperature range is
-40°C to +85°C.
Features
• 8-bit, 256-Step, Adjustable Sink Current Output
• 60MHz VCOM Buffer/Amplifier
• 4.5V to 19.0V Analog Supply Range for Normal Operation
(10.8V Minimum Analog Supply Voltage for Programming)
• 2.25V to 3.6V Logic Supply Voltage Operating Range
• 400kHz, I2C Interface
• On-Chip 8-Bit EEPROM
• Guaranteed Monotonic Over-Temperature
• Compatible with applications using the 7-bit ISL45041
• Pb-free (RoHS-compliant)
• Ultra-Thin 10 Ld TDFN (3 x 3 x 0.8mm max)
Applications
• LCD Panel VCOM Generator
• Electrophoretic Display VCOM Generator
Related Literature
• AN1627 “ISL24211IRTZ-EVALZ Evaluation Board User Guide”
Typical Application
3.3V
VDD
AVDD
MICRO-
CONTROLLER
I2C
PORT
I/O PIN
February 23, 2011
FN7585.0
1
7
SDA
8
SCL
4
WP
63
2
DVR_OUT
ISL24211
1
INN
10
VCOM_OUT
9
SET
5
R1
R2
RSET
FIGURE 1. TYPICAL ISL24211 APPLICATION
LCD PANEL
VCOM
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.




ISL24211 pdf, 반도체, 판매, 대치품
ISL24211
Absolute Maximum Ratings
Supply Voltage
AVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
Input Voltage with respect to Ground
SET, INN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
SCL, SDA and WP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..VDD + 0.3V
Output Voltage with respect to Ground
DVR_OUT, VCOM_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD
Continuous Output Current
DVR_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
VCOM_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100mA
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 2kV
Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
10 Ld TDFN Package (Notes 4, 5) . . . . . . .
53
11
Moisture Sensitivity (see Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Range
AVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5), VCOM_OUT pin
connected to INN, unless otherwise specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
MAX
TYP (Note 6) UNITS
DC CHARACTERISTICS
VDD
AVDD
AVDD
VDD Supply Range - Operating
AVDD Supply Range Supporting EEPROM Programming
AVDD Supply Range for Wide-Supply Operation
(not supporting EEPROM Programming)
2.25
10.8
4.5
3.6 V
19 V
19 V
IDD VDD Supply Current
IAVDD AVDD Supply Current
DVR_OUT CHARACTERISTICS
WP = SCL = SDA = VDD
WP = SCL = SDA = VDD
95 300
3.8 6.5
µA
mA
ZSESET
FSESET
TCVSET
VDVR_OUT
IDVR_OUT
INL
SET Zero-Scale Error
SET Full-Scale Error
SET Voltage Drift
DVR_OUT Voltage Range
Maximum DVR_OUT Sink Current
Integral Non-Linearity
IDVR_OUT < 0.5mA
VSET + 0.4
7
4
±3
±8
AVDD
±2
LSB
LSB
µV/°C
V
mA
LSB
DNL Differential Non-Linearity
±1 LSB
OUTPUT AMPLIFIER CHARACTERISTICS
VOS
TCVOS
IB
CMRR
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Common-Mode Rejection Ratio
±2 ±15 mV
-6.3 µV/°C
0.001
±1
µA
55 75
dB
PSRR Power Supply Rejection Ratio
60 82
dB
AVOL
VOL
Open Loop Gain
Output Swing Low
IL = -5mA
55 75
dB
50 150 mV
4 FN7585.0
February 23, 2011

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ISL24211 전자부품, 판매, 대치품
ISL24211
The maximum value of IDVR_OUT can be calculated by
substituting the maximum register value of 255 into Equation 2,
resulting in Equation 3:
IDVROUT(MAX) = 2----A0----VR---D-S---D-E---T-
(EQ. 3)
Equation 2 can also be used to calculate the unit sink current
step size per Register Code, resulting in Equation 4:
ISTEP = -(--2---5----6----)--A(---2-V--0--D--)--D-(--R----S----E---T---)
(EQ. 4)
Determination of RSET
The ultimate goal for the ISL24211 is to generate an adjustable
voltage between two endpoints, VCOM_MIN and VCOM_MAX, with
a fixed power supply voltage, AVDD. This is accomplished by
choosing the correct values for RSET, R1 and R2. The exact value
of RSET is not critical. Values from 1k to more than 100k will
work under most conditions. The following expression calculates
the minimum RSET value:
RSET(MIN)
=
⎝⎛---V----O---U----T---(--M--A-------I1-V---N----6D---)-----D--–-----A--------2-V-------0D--------D-----⎠⎞-⎠⎟⎟⎟⎟⎞
(k
Ω)
(EQ. 5)
Note that this is the absolute minimum value for RSET. Larger
RSET values reduce quiescent power, since R1 and R2 are
proportional to RSET. The ISL24211 is tested with a 5kΩ RSET.
Determination of R1 and R2
With AVDD, VCOM(MIN) and VCOM(MAX) known and RSET chosen
per the above requirements, R1 and R2 can be determined using
Equations 6 and 7:
R1
=
5120
RSE
T
2----5----6V----C---O-V---MC---O-(--M-M----A-(--M-X---)-A--–-X----)V---–C----OV---M-C---O-(--M-M----I-(-N-M--)--I--N----)⎠⎟⎞
(EQ. 6)
R2
=
5120
RSE
T
-2---5----5--------A----V---D---V-D---C--+-O----VM---C--(--MO----MA----X(--M-)---–-I--N--V-)--C--–--O--2--M--5--(-6-M-----I--NV----)C---O----M-----(--M----A----X---)⎠⎟⎞
(EQ. 7)
Final Transfer Function
The voltage at DVR_OUT can be calculated from Equation 8:
VDVROUT
=
AVDD
--R----1-R--+--2--R-----2--⎠⎟⎞
1
R-----e---g----i--s---t---e-2--r-5--V--6-a----l--u----e----+-----1--
2----0---R-R---1-S----E---T-⎠⎟⎞⎠⎟⎞
(EQ. 8)
With amplifier A2 in the unity-gain configuration (VCOM_OUT tied
to INN as shown in Figure 5), VDVROUT = VCOM_OUT = VCOM.
Example
As an example, suppose the AVDD supply is 15V, the desired
VCOM_MIN= 6.5V and the desired VCOM_MAX = 8.5V. RSET is
arbitrarily chosen to be 7.5kΩ.
First, verify that our chosen RSET meets the minimum
requirement described in Equation 5:
( 7.5 k Ω )
>
RSE
T
(MIN
)
=
⎝⎛---6----.-5----V11--------56--–------12-------50------⎠⎞-⎠⎟⎟⎟⎞
=
0.163
k
Ω⎟
(EQ. 9)
Using Equations 6 and 7, calculate the values of R1 and R2:
R1
=
5120
7500
-2---5----6-8----.-5--8--–-.-5-6----.-–5----6----.-5--⎠⎞
=
35.4 k Ω
(EQ. 10)
R2
=
5120
7500
2----5----5--------1---5---8--+--.-5--6---–-.-5---6--–-.--5--2---5----6--------8---.-5-- ⎠⎞
=
46.4 k Ω
(EQ. 11)
Table 1 shows the resulting VCOM voltage as a function of register
value for these conditions.
TABLE 1. EXAMPLE VDVR_OUT vs REGISTER VALUE
REGISTER VALUE
0
VDVR_OUT (V)
8.49
20 8.34
40 8.18
60 8.02
80 7.87
100 7.71
120 7.55
127 7.50
140 7.40
160 7.24
180 7.09
200 6.93
220 6.77
240 6.62
255 6.50
Output Voltage Span Calculation
It is also possible to calculate VCOM(MIN) and VCOM(MAX) from the
existing resistor values.
VCOM_MIN occurs when the greatest current, IDVR(MAX), is drawn
from the middle node of the R1/R2 divider. Substituting
RegisterValue = 255 into Equation 8 gives the following:
VCOM(MIN)
=
A
VD D ⎝⎜⎛
--R----1-R--+--2--R-----2--⎠⎟⎞
1
2----0---R-R---1-S----E---T-⎠⎟⎞
(EQ. 12)
Similarly, RegisterValue = 0 for VCOM(MAX):
VCOM(MAX)
=
A
VD
D ⎝⎜
--R----1-R--+--2--R-----2--⎠⎟⎞
1
2----51----6-
2----0---R-R---1-S----E---T-⎠⎟⎞
(EQ. 13)
7 FN7585.0
February 23, 2011

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