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EZR32LG330 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 EZR32LG330
기능 Wireless MCUs
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EZR32LG330 데이터시트, 핀배열, 회로
EZR32LG Wireless MCUs
EZR32LG330 Data Sheet
EZR32LG330 Wireless MCU family with ARM Cortex-M3 CPU,
USB, and sub-GHz Radio
The EZR32LG Wireless MCUs are the latest in Silicon Labs family of wireless MCUs de-
livering a high performance, low energy wireless solution integrated into a small form
factor package. By combining a high performance sub-GHz RF transceiver with an ener-
gy efficient 32-bit MCU, the EZR32LG family provides designers the ultimate in flexibility
with a family of pin-compatible devices that scale with 64/128/256 kB of flash and sup-
port Silicon Labs EZRadio or EZRadioPRO transceivers. The ultra-low power operating
modes and fast wake-up times of the Silicon Labs energy friendly 32-bit MCUs, com-
bined with the low transmit and receive power consumption of the sub-GHz radio, result
in a solution optimized for battery powered applications.
32-Bit ARM Cortex wireless MCUs applications include the following:
• Energy, gas, water and smart metering
• Health and fitness applications
• Consumer electronics
• Alarm and security systems
• Building and home automation
KEY FEATURES
• Silicon Labs’ first 32-bit Wireless MCUs
• Based on ARM Cortex M3 (LG) and M4
(WG) CPU cores with 256 kB of flash and
32 kB RAM
• Best-in-class RF performance with EZradio
and EZRadioPro transceivers
• Ultra-low power wireless MCU
• Low transmit and receive currents
• Ultra-low power standby and sleep
modes
• Fast wake-up time
• Low Energy sensor interface (LESENSE)
• Rich set of peripherals including 12-bit ADC
and DAC, multiple communication
interfaces (USB, UART, SPI, I2C), multiple
GPIO and timers
• AES Accelerator with 128/256-bit keys
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EZR32LG330 pdf, 반도체, 판매, 대치품
3. System Overview
EZR32LG330 Data Sheet
System Overview
3.1 Introduction
The EZR32LG330 Wireless MCUs are the latest in Silicon Labs family of wireless MCUs delivering a high performance, low energy
wireless solution integrated into a small form factor package. By combining a high performance sub-GHz RF transceiver with an energy
efficient 32-bit ARM Cortex-M3, the EZR32LG family provides designers with the ultimate in flexibility with a family of pin-compatible
parts that scale from 64 to 256 kB of flash and support Silicon Labs EZRadio or EZRadioPRO transceivers. The ultra-low power operat-
ing modes and fast wake-up times combined with the low transmit and receive power consumption of the sub-GHz radio result in a
solution optimized for low power and battery powered applications. For a complete feature set and in-depth information on the modules,
the reader is referred to the EZR32LG Reference Manual.
The EZR32LG330 block diagram is shown below.
Figure 3.1. Block Diagram
3.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection
Unit with support for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts triggered while
the CPU is asleep. The EZR32 implementation of the Cortex-M3 is described in detail in EZR32 Cortex-M3 Reference Manual.
3.1.2 Debugging
These devices include hardware debug support through a 2-pin serial-wire debug interface and an Embedded Trace Module (ETM) for
data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data
trace and software-generated messages.
3.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EZR32LG microcontroller. The flash memory is readable and
writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks: the main block and the information block.
Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock
bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations
are supported in the energy modes EM0 and EM1.
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EZR32LG330 전자부품, 판매, 대치품
EZR32LG330 Data Sheet
System Overview
3.1.25 Operational Amplifier (OPAMP)
The EZR32LG330 features 2 Operational Amplifiers. The Operational Amplifier is a versatile general purpose amplifier with rail-to-rail
differential input and rail-to-rail single ended output. The input can be set to pin, DAC or OPAMP, whereas the output can be pin,
OPAMP or ADC. The current is programmable and the OPAMP has various internal configurations such as unity gain, programmable
gain using internal resistors, etc.
3.1.26 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface (LESENSE), is a highly configurable sensor interface with support for up to 16 individually configu-
rable sensors. By controlling the analog comparators and DAC, LESENSE is capable of supporting a wide range of sensors and meas-
urement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a pro-
grammable FSM which enables simple processing of measurement results without CPU intervention. LESENSE is available in energy
mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy budget.
3.1.27 Backup Power Domain
The backup power domain is a separate power domain containing a Backup Real Time Counter, BURTC, and a set of retention regis-
ters, available in all energy modes. This power domain can be configured to automatically change power source to a backup battery
when the main power drains out. The backup power domain enables the EZR32LG330 to keep track of time and retain data, even if the
main power source should drain out.
3.1.28 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data
block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB slave
which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations (i.e., 8- or
16-bit operations are not supported).
3.1.29 General Purpose Input/Output (GPIO)
In the EZR32LG330, there are 38 General Purpose Input/Output (GPIO) pins, which are divided into ports with up to 16 pins each.
These pins can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive
strength can also be configured individually for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Tim-
er PWM outputs or USART communication, which can be routed to several locations on the device. The GPIO supports up to 16 asyn-
chronous external pin interrupts, which enables interrupts from any pin on the device. Also, the input value of a pin can be routed
through the Peripheral Reflex System to other peripherals.
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Wireless MCUs

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