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부품번호 | EM78P247B 기능 |
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기능 | 8-BIT MICRO-CONTROLLER | ||
제조업체 | EMC | ||
로고 | |||
DESCRIPTION
EM78P247/447A/B/C
8-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
The EM78P247/447A/B/C is an 8-bit microprocessor with low-power, high speed CMOS technology. There
are 4Kx13 bits Electical One Time Programmable Read Only Memory (OTP-ROM) within it. It provides 1
Protect bit and 6 One-time Programmable Option bits to protect the OTP memory code from any external access
as well as the user's options.
The OTP ROM will be incorporated into EM78P247/447A/B/C 8-bit microcontroller instead of it's original
memory. The user's development program can be easily programmed into or verify from this OTP memory by
using EMC OTP PROGRAMMER.
FEATURES
• Operating voltage range: 2.5V~5.5V
• Available in temperature range: 0°C~70°C
• Operating frequency range:
Crystal Type: DC~20MHz at 5V
DC~8MHz at 3V
RC Type:
DC~4MHz at 5V
DC~4MHz at 3V
• 2Kx13 on chip ROM (EM78267A/B/C)
• 4Kx13 on chip ROM (EM78467A/B/C)
• 9 special function registers
• 148x8 general purpose registers (SRAM)
• 3 bi-directional tri-state I/O ports (20 I/O pins for EM78P247/447A) (24 I/O pins for EM78P247/447B)
(22 I/O pins for EM78247/447C)
• 5 level stack for subroutine nesting
• 8-bit real time clock/counter (TCC) with selective signal sources and trigger edges, and with overflow interrupt
• Selectable oscillator options:
XTAL1 type (High frequency)
XTAL2 type (32.768KHz)
RC type
External clock input
• Two oscillator periods per instruction cycle
• Power down mode
• Programmable wake up from sleep circuit on I/O ports
• Programmable free running on-chip watchdog timer
• Ten pull-up and wake-up pins
• Two open-drain pins
• Two R-option pins
• Interrupt function available
• 28 pin DIP, SOIC, SSOP
(EM78P247/447A)
28 pin SOIC
(EM78P247/447C)
* This specification are subject to be changed without notice.
9.30.1997 1
EM78P247/447A/B/C
8-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
R2 (Program Counter) & Stack
• Depending on the device type, R2 and hardware stack are 12 bits wide. The structure is depicted in Fig. 3.
• Generates 4Kx13 on-chip ROM addresses to the relative programming instruction codes. One program page
is 1K words long.
• R2 is set all “1”s upon a RESET condition.
• “JMP” instruction allows the direct loading of the lower 10 program counter bits. Thus, “JMP” allows jump
to any location on one page.
• “CALL” instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the
subroutine entry address can be any location on one page.
• “RET” (“RETL k”, “RETI”) instruction loads the program counter with the contents at the top of stack.
• “MOV R2,A” allows the loading of an address from the “A” register to the lower 8 bits of PC, and the ninth
and tenth bits (A8~A9) of PC are cleared.
• “ADD R2,A” allows a relative address be added to the current PC, and the ninth and tenth bits of PC are cleared.
• Any instruction which writes to R2 (e.g. “ADD R2,A”, “MOV R2,A”, “BC R2,6”,) (except “TBL”) will cause
the ninth and tenth bits (A8~A9) of PC to be cleared. Thus, the computed jump is limited to the first 256
locations of any program page.
• “TBL” allows a relative address be added to the current PC (R2+AR→2), and contents of the ninth and tenth
bits (A8~A9) of PC are not changed. Thus, the computed jump can be on the second (or third, 4th) 256 locations
on one program page.
• In case of EM78P247/447, the most significant bits (A10~A11) will be loaded with the contents of bits PS0~PS1
in the status register (R3) upon the execution of a “JMP”, “CALL”, or any instruction which writes to R2.
EM78P447
EM78P247/447
CALL
PC A11 A10 A9 A8
A7 ~ A0
RET
RTTL
RETI
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
000
00
Page 0
001: Hareware interrupt location
002: Software interrupt (INT instruction) location
FFF: Reset location
3FF
400
01 Page 1
7FF
800
EM78P247
10 Page 2
BFF
C00
11
Page 3
FFF
EM78P447
Fig. 3 Program counter organization
* This specification are subject to be changed without notice.
9.30.1997 4
4페이지 EM78P247/447A/B/C
8-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
• IOCF is the interrupt mask register.
• Note that reading R3F by instruction will get the result of “logic AND” of R3F and IOCF.
Special Purpose Registers
A (Accumulator)
• Internal data transfer, or instruction operand holding
• It’s not an addressable register.
CONT (Control Register)
7
6543
2
10
PHEN INT TS TE PAB PSR2 PSR1 PSR0
• Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2
0
0
0
0
1
1
1
1
PSR1
0
0
1
1
0
0
1
1
PSR0
0
1
0
1
0
1
0
1
TCC Rate
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
WDT Rate
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
• Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
• Bit 4 (TE) TCC signal edge
0: increment from low to high transition on TCC pin
1: increment from high to low transition on TCC pin
• Bit 5 (TS) TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
• Bit 6 (INT) Interrupt enable flag which cannot be written by CONTW instruction.
0: interrupt masked by DISI or hardware interrupt.
1: interrupt enabled by ENI/RETI instruction.
• Bit 7 (/PHEN) I/O pin pull-high enable flag
0: P60~P67 and P74~P75 have internal pull-high.
1: pull-high is disabled.
* This specification are subject to be changed without notice.
9.30.1997 7
7페이지 | |||
구 성 | 총 20 페이지수 | ||
다운로드 | [ EM78P247B.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
EM78P247 | 8-BIT MICRO-CONTROLLER | EMC |
EM78P247A | 8-BIT MICRO-CONTROLLER | EMC |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |