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SL2305 데이터시트 PDF




Silicon Laboratories에서 제조한 전자 부품 SL2305은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 SL2305 기능
기능 Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer
제조업체 Silicon Laboratories
로고 Silicon Laboratories 로고


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SL2305 데이터시트, 핀배열, 회로
SL2305
Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)
Key Features
10 to 140 MHz operating frequency range
Low output clock jitter:
- 140 ps-max c-c-j at 66 MHz
Low output-to-output skew: 150 ps-max
Low product-to-product skew: 400 ps-max
3.3 V power supply range
Low power dissipation:
- 14 mA-max at 66MHz
- 26 mA-max at 133 MHz
One input drives 5 outputs organized as 4+1
SpreadThru™ PLL that allows use of SSCG
Standard and High-Drive options
Available in 8-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
Applications
Printers and MFPs
Digital Copiers
PCs and Work Stations
DTV
Routers, Switchers and Servers
Digital Embeded Systems
Description
The SL2305 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to five (5) clock
outputs from one (1) reference input clock for high speed
clock distribution applications. The product has an on-chip
PLL which locks to the input clock at CLKIN and receives its
feedback internally from the CLKOUT pin.
The SL2305 is available with two (2) drive strength versions.
The -1 is the standard-drive version and -1H is the high-
drive version.
The SL2305 high-drive version operates up to 140MHz and
the standard drive version -1 operates up to 100.
The SL2305 enter into Power-Down (PD) mode if the input
at CLKIN is DC (0 to VDD). In this power-down state all five
(5) outputs are tri-stated and the PLL is turned off leading to
less than 12μA-max of power supply current draw.
Benefits
Up to five (5) distribution of input clock
Standard and High-Drive levels to control impedance
level, frequency range and EMI
Low jitter and skew
Low power dissipation
Low cost
Block Diagram
CLKIN
PLL
VDD
GND
CLKOUT
CLK1
CLK2
CLK3
CLK4
Rev 2.1, October 22, 2007
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
Page 1 of 11
www.silabs.com




SL2305 pdf, 반도체, 판매, 대치품
SL2305
Absolute Maximum Ratings
Description
Supply voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
ESD Rating (Human Body Model)
ESD Rating (Charge Device Model)
ESD Rating (Machine Model)
Latch-up
Condition
In operation, C-Grade
In operation, I-Grade
No power is applied
In operation, power is applied
JEDEC22-A114D
JEDEC22-C101C
JEDEC22-A115D
125°C
Min
– 0.5
– 0.5
0
– 40
– 65
-4,000
-1,500
-250
-200
Max
4.6
VDD+0.5
70
85
150
125
260
4,000
1,500
250
200
Unit
V
V
°C
°C
°C
°C
°C
V
V
V
mA
Operating Conditions: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades
Symbol
Description
Condition
Min Max
VDD
3.3V Supply Voltage
3.3V+/-10%
3.0 3.6
TA Operating
Temperature(Ambient)
Commercial
Industrial
0 70
–40 85
CLOAD Load Capacitance
10 to 140 MHz, -1H high drive
– 15
10 to 100 MHz, -1H high drive
– 30
10 to 100MHz, -1 standard drive
– 15
10 to 66MHz, -1 standard drive
– 30
CIN Input Capacitance
CLKIN pin
–7
tpu Power-up Time
Power-up time for all VDDs to reach
minimum VDD voltage (VDD=3.0V).
0.05
100
CLBW
Closed-loop bandwidth
3.3V, (typical)
1.2
ZOUT
Output Impedance
3.3V (typical), -1H high drive
22
3.3V (typical), -1 standard drive
32
Unit
V
°C
°C
pF
pF
pF
pF
pF
ms
MHz
Rev 2.1, October 22, 2007
Page 4 of 11

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SL2305 전자부품, 판매, 대치품
External Components & Design Considerations
Typical Application Schematic
SL2305
CLKIN
VDD
0.1μF
18
63
SL2305
4
GND
7
CLKOUT
CL
CLK1
CL
CLK4
CL
Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1μF must be used between VDD and VSS on the pins 6 and 4. Place
the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to
the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs and the
load is over 1 ½ inch. The nominal impedance of the Clock outputs are about 30 Ω. Use 20 Ω resistor in series with the
output to terminate 50Ω trace impedance and place 20 Ω resistor as close to the clock outputs as possible.
Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay”
between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for internal feedback to
PLL, and sees an additional 2 pF load with respect to the clock pins. For applications requiring zero input/output delay, the
load at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance
at the CLKOUT pin could be increased or decreased to increase or decrease the delay between clocks and CLKIN.
For minimum pin-to-pin skew, the external load at the clock outputs must be the same.
Rev 2.1, October 22, 2007
Page 7 of 11

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