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PDF SL23EP05 Data sheet ( Hoja de datos )
| Número de pieza | SL23EP05 | |
| Descripción | LOW JITTER AND SKEW 10 TO 220 MHZ ZERO DELAY BUFFER | |
| Fabricantes | Silicon Laboratories | |
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SL23EP05
LOW JITTER AND SKEW 10 TO 220 MHZ ZERO DELAY
BUFFER (ZDB)
Features
10 to 220 MHz operating
Low power dissipation:
frequency range
16 mA-max at 66 MHz and
Low output clock jitter:
VDD = 3.3 V
50 ps-typ cycle-to-cycle jitter
20 ps-typ period jitter
Low output-to-output skew:
30 ps-typ
14 mA-max at 66 MHz and
VDD = 2.5 V
One input drives five outputs
organized as 4+1
Low product-to-product skew:
60 ps-typ
SpreadThru™ PLL that allows
use of SSCG
Wide 2.5 V to 3.3 V power supply Standard and High-Drive options
range
Available in 8 pin SOIC and
TSSOP packages
Available in Commercial and
Industrial grades
Ordering Information:
See page 14.
Applications
Printers and MFPs
Digital Copiers
PCs and Work Stations
Routers, Switchers and Servers
Digital Embedded Systems
Pin Assignments
SL23EP05
Benefits
Up to five distribution of input
clock
Low power dissipation, jitter and
skew
Standard and High-Drive levels Low cost
to control impedance level,
frequency range and EMI
Description
The SL23EP05 is a low skew, low jitter, and low power Zero Delay Buffer
(ZDB) designed to produce up to five clock outputs from one reference input
clock for high speed clock distribution applications. The product has an on-
chip PLL which locks to the input clock at CLKIN and receives its feedback
internally from the CLKOUT pin.
The SL23EP05 is available with two drive strength versions called –1 and
–1H. The –1 is the standard-drive version and –1H is the high-drive version.
The SL23EP05 high-drive version operates up to 220 MHz and 180 MHz at
3.3 V and 2.5 V power supplies, respectively. The standard drive version –1
operates up to 200 MHz and 167 MHz at 3.3 V and 2.5 V, respectively.
The SL23EP05 enter into Power Down (PD) mode if the input at CLKIN is
less then 2.0 MHz or there is no rising edge. In this state all five outputs are
tri-stated and the PLL is turned off leading to less than 10 μA of power
supply current draw.
Patents pending
Rev. 2.2 5/15
Copyright © 2015 by Silicon Laboratories
SL23EP05
1 page  
SL23EP05
Table 3. AC Electrical Specifications (VDD = 3.3 V and 2.5 V)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Maximum Frequency
(Input=Output) 1
FMAX
3.3 V High Drive
3.3 V Standard Drive
10 — 220 MHz
10 — 200 MHz
2.5 V High Drive
10 — 180 MHz
2.5 V Standard Drive
10 — 167 MHz
Input Duty Cycle
Output Duty Cycle 2
Rise, Fall Time (3.3V)
Measured at:
0.8 to 2.0 V 2
INDC
OUTDC
tr/f3.3
<135 MHz, VDD = 3.3 V
<135 MHz, VDD = 2.5 V
<135 MHz, VDD = 3.3 V
<135 MHz, VDD = 2.5 V
High drive, CL = 15 pF, >135 MHz
Std drive, CL = 15 pF, <170 MHz
High drive, CL = 30 pF, <100 MHz
25 — 75 %
40 — 60 %
45 — 55 %
40 — 60 %
— — 0.5 ns
— — 1.5 ns
— — 1.5 ns
Rise, Fall Time (2.5) 2
Measured at: 0.6 to 1.8 V
tr/f2.5
Std drive, CL = 30 pF, <100 MHz
High drive, CL = 15 pF, >135 MHz
Std drive, CL = 15 pF, <135 MHz
— — 2.5 ns
— — 1.5 ns
— — 2.5 ns
Output-to-Output Skew 2
t1
High drive, CL = 30 pF, <100 MHz
— — 2.5 ns
All outputs CL = 0, 3.3 V supply,
— 30 90 ps
2.5 V power supply, standard drive
All outputs CL = 0, 2.5 V power supply,
high drive
—
40 100 ps
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
Edge 2
t2
PLL enabled @ 3.3 V
PLL enabled @2.5 V
–100 — 100 ps
–200 — 200 ps
Part-to-Part Skew 2
t3 Measured at VDD/2. Any output to any –150 — 150 ps
output, 3.3 V supply
Measured at VDD/2. Any output to any –300 — 300 ps
output, 2.5 V supply
Notes:
1. For the given maximum loading conditions. See CL in Operating Conditions Table.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Rev. 2.2
5
5 Page 
8.2. Switching Waveforms
SL23EP05
Figure 2. Output to Output Skew
Figure 3. Input to Output Skew
Figure 4. Part-to-Part Skew
Rev. 2.2
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet SL23EP05.PDF ] | |
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