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Número de pieza | SL23EP09 | |
Descripción | Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer | |
Fabricantes | Silicon Laboratories | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de SL23EP09 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
No Preview Available ! SL23EP09
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
Key Features
• 10 to 220 MHz operating frequency range
• Low output clock skew: 45ps-typ
• Low output clock jitter:
50 ps-typ cycle-to-cycle jitter
20 ps-typ period jitter
• Low part-to-part output skew: 90 ps-typ
• Wide 2.5 V to 3.3 V power supply range
• Low power dissipation:
26 mA-max at 66 MHz and VDD=3.3 V
24 mA-max at 66 MHz and VDD=2.5V
• One input drives 9 outputs organized as 4+4+1
• Select mode to bypass PLL or tri-state outputs
• SpreadThru™ PLL that allows use of SSCG
• Standard and High-Drive options
• Available in 16-pin SOIC and TSSOP packages
• Available in Commercial and Industrial grades
Applications
• Printers, MFPs and Digital Copiers
• PCs and Work Stations
• Routers, Switchers and Servers
• Digital Embeded Systems
Block Diagram
Description
The SL23EP09 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to nine (9) clock
outputs from one (1) reference input clock, for high speed
clock distribution applications.
The product has an on-chip PLL which locks to the input
clock at CLKIN and receives its feedback internally from the
CLKOUT pin.
The SL23EP09 has two (2) clock driver banks each with four
(4) clock outputs. These outputs are controlled by two (2)
select input pins S1 and S2. When only four (4) outputs are
needed, four (4) bank-B output clock buffers can be tri-stated
to reduce power dissipation and jitter. The select inputs can
also be used to tri-state both banks A and B or drive them
directly from the input bypassing the PLL and making the
product behave like a Non-Zero Delay Buffer (NZDB).
The high-drive version operates up to 220MHz and 200MHz
at 3.3V and 2.5V power supplies respectively.
Benefits
• Up to nine (9) distribution of input clock
• Standard and High-Dirive levels to control impedance
level, frequency range and EMI
• Low power dissipation, jitter and skew
• Low cost
CLKIN
Low Power and
Low Jitter
PLL
MUX
S2
Input Selection
Decoding Logic
S1
2
VDD
2
GND
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Rev 2.0, May 12, 2008
2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500
1+(512) 416-9669
Page 1 of 14
www.silabs.com
1 page Absolute Maximum Ratings
Description
Supply voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
ESD Rating (Human Body Model)
ESD Rating (Change Device Model)
ESD Rating (Machine Model)
Condition
In operation, C-Grade
In operation, I-Grade
No power is applied
In operation, power is applied
JEDECCC22-A114D
JEDECCC22-C101C
JEDECCC22-A115D
SL23EP09
Min.
– 0.5
– 0.5
0
– 40
– 65
–
–
-4000
-1500
-200
Max.
4.6
VDD+0.5
70
85
150
125
260
4000
1500
200
Unit
V
V
°C
°C
°C
°C
°C
V
V
V
Rev 2.0, May 12, 2008
Page 5 of 14
5 Page Switching Waveforms
OUTPUT
VDD/2
OUTPUT
t1
VDD/2
Figure 2. Output to Output Skew
INPUT
VDD/2
CLKOUT
t2
VDD/2
Figure 3. Input to Output Skew
Any Output
Part 1 or 2
VDD/2
Any Output
Part 2 or 1
t3
VDD/2
Figure 4. Part-to-Part Skew
Rev 2.0, May 12, 2008
SL23EP09
Page 11 of 14
11 Page |
Páginas | Total 14 Páginas | |
PDF Descargar | [ Datasheet SL23EP09.PDF ] |
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