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PDF Si88321 Data sheet ( Hoja de datos )
| Número de pieza | Si88321 | |
| Descripción | DUAL DIGITAL ISOLATORS | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si88x2x
DUAL DIGITAL ISOLATORS WITH DC-DC CONVERTER
Features
High-speed isolators with
Highly-reliable: 100 year lifetime
integrated dc-dc converter
High electromagnetic immunity and
Fully-integrated secondary sensing ultra-low emissions
feedback-controlled converter with RoHS compliant packages
dithering for low EMI
SOIC-20 wide body
dc-dc converter peak efficiency of SOIC-16 wide body
83% with external power switch Isolation of up to 5000 Vrms
Up to 5 W isolated power with High transient immunity of
external power switch
100 kV/µs (typical)
Options include dc-dc shutdown, AEC-Q100 qualified
frequency control, and soft start Wide temp range
Standard Voltage Conversion
–40 to +125 °C
3/5 V to isolated 3/5 V
24 V to isolated 3/5 V supported
Precise timing on digital isolators
0–100 Mbps
18 ns typical prop delay
Applications
Industrial automation systems
Hybrid electric and electric
vehicles
Isolated power supplies
Inverters
Data acquisition
Motor control
PLCs, distributed control systems
Safety Approval (Pending)
UL 1577 recognized
Up to 5000 Vrms for 1 minute
CSA component notice 5A
approval
VDE certification conformity
VDE0884-10
CQC certification approval
GB4943.1
Description
The Si88xx integrates Silicon Labs’ proven digital isolator technology with an
on-chip isolated dc-dc converter that provides regulated output voltages of
3.3 or 5.0 V (or >5 V with external components) at peak output power levels
of up to 5 W. These devices provide up to two digital channels. The dc-dc
converter has user-adjustable frequency for minimizing emissions, a soft-start
function for safety, a shutdown option and loop compensation. The device
requires only minimal passive components and a miniature transformer.
The ultra-low-power digital isolation channels offer substantial data rate,
propagation delay, size and reliability advantages over legacy isolation
technologies. Data rates up to 100 Mbps max are supported, and all devices
achieve propagation delays of only 23 ns max. Ordering options include a
choice of dc-dc converter features, isolation channel configurations and a fail-
safe mode. All products are certified by UL, CSA, VDE, and CQC.
Ordering Information:
See page 36.
Pin Assignments
See page 31
GNDP 1
RSN 2
ESW 3
VDDA 4
GNDA 5
VREGA 6
SH_FC 7
SS 8
A1 9
HF
XMTR
HF
RCVR
A2 10 HF
XMTR
HF
RCVR
Si88620
Patents pending
20 GNDB
19 VDDB
18 VREGB
17 NC
16 VSNS
15 COMP
14 NC
13 NC
12 B1
11 B2
Rev. 0.5 7/15
Copyright © 2015 by Silicon Laboratories
Si88x2x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
1 page  
Si88x2x
Table 2. Electrical Characteristics1 (Continued)
VIN = 24 V; VDDA = VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8822x/32x; VDDA = 4.3 V (see Figure 3) for all Si8842x/62x;
TA = –40 to 125 °C unless otherwise noted.
Parameter
No Load Supply Cur-
rent IDDP
Si8842x, Si8862x
No Load Supply Cur-
rent IDDA
Si8842x, Si8862x
Symbol
IDDPQ_DCDC3
IDDAQ_DCDC4
Test Condition
See Figure 3
VIN = 24 V
See Figure 3
VIN = 24 V
Min Typ Max Unit
0.8 mA
5.8 mA
Peak Efficiency
Si8822x, Si8832x
Si8842x, Si8862x
See Figure 2
See Figure 3
%
78
83
Voltage Regulator
Reference Voltage
Si8842x, Si8862x
VREGA, VREGB
IREG = 600 µA
See Figure 24 for typical I–V
curve
4.8
V
VREG tempco
KTVREG
–0.43
mV/°C
VREG input current
IREG
350 — 950 µA
Soft start time,
full load
Si8822x, Si8842x
Si8832x, Si8862x
tSST See Figures 19–22 for typical
soft start times over load con-
ditions.
25
50
ms
Restart Delay from
fault event
tOTP
21 s
Digital Isolator
VDD Undervoltage
Threshold
VDDUV+
VDDA, VDDB rising
2.7 V
VDD Undervoltage
Threshold
VDDUV–
VDDA, VDDB falling
2.6 V
VDD Undervoltage
Hysteresis
VDDHYS
100 mV
Positive-Going Input
Threshold
VT+
All inputs rising
1.67 V
Notes:
1. Over recommended operating conditions as noted in Table 1.
2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset
3. VDDP current needed for dc-dc circuits.
4. VDDA current needed for dc-dc circuits.
5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output.
Rev. 0.5
5
5 Page 
Si88x2x
Table 2. Electrical Characteristics1 (Continued)
VIN = 24 V; VDDA = VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8822x/32x; VDDA = 4.3 V (see Figure 3) for all Si8842x/62x;
TA = –40 to 125 °C unless otherwise noted.
Parameter
Symbol
Test Condition
Min Typ Max Unit
Channel-Channel
Skew
tPSK
— 1.0
ns
Output Rise Time
tr
CL = 15 pF
2.5 ns
Output Fall Time
tf
CL = 15 pF
2.5 ns
Common Mode
Transient Immunity
Startup Time7
CMTI
tSU
VI = VDDx or 0 V
VCM = 1500 V (See Figure 4)
40
100
55
kV/µs
µs
Notes:
1. Over recommended operating conditions as noted in Table 1.
2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset
3. VDDP current needed for dc-dc circuits.
4. VDDA current needed for dc-dc circuits.
5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output.
1.4 V
Input
tPLH
tPHL
1.4 V
Output
90%
10%
90%
10%
tr tf
Figure 1. Propagation Delay Timing for Digital Channels
Rev. 0.5
11
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| PDF Descargar | [ Datasheet Si88321.PDF ] | |
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