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PDF ZL2102 Data sheet ( Hoja de datos )
| Número de pieza | ZL2102 | |
| Descripción | 6A Digital Integrated Synchronous Step-Down DC/DC Regulator | |
| Fabricantes | Intersil | |
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DATASHEET
6A Digital Integrated Synchronous Step-Down DC/DC
Regulator with Auto Compensation
ZL2102
The ZL2102 is an integrated digital power regulator with auto
compensation and power management functions in a small
package, resulting in a flexible and integrated solution, which
can be configured using the PowerNavigator™ graphical user
interface. This synchronous buck converter operates from a
4.5V to 14V input supply and provides from 0.54V to 5.5V
output voltage at up to 6A.
The ZL2102 can be configured for most applications using only
hardware pin straps to adjust switching frequency, output
voltage, UVLO, soft-start ramp/delay settings, sequencing
options, and SMBus address. For more advanced
configurations, the ZL2102 supports over 70 PMBus
commands. Output voltage/current is factory calibrated.
Internal synchronous power MOSFETs enable the ZL2102 to
deliver continuous loads up to 6A with high efficiency. An
internal Schottky bootstrap diode reduces discrete component
count. The ZL2102 also supports phase spreading to reduce
system input capacitance.
The ZL2102 uses the SMBus™ with PMBus™ protocol for
communication with a host controller and the Intersil's
proprietary Digital-DC™ bus for interoperability between other
Intersil devices.
Features
• Integrated MOSFET switches
• 6A continuous output current
• Adjustable 0.54V to 5.5V output range
• 4.5V to 14V input range
• Up to 90% efficiency
• Auto compensation for fast transient response
• SMBus compliant serial interface
• Snapshot™ parametric capture
• Internal nonvolatile memory
• Small footprint QFN package (6mmx6mm)
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
Related Literature
• AN2010 "Thermal and Layout Guidelines for Digital-DC™
Products"
• AN2035 "Compensation Using CompZL™"
• TB389 "PCB Land Pattern and Surface Mount Guidelines for
QFN Packages"
INTERFACE
HARDWARE
CONTROL
HARDWARE
CONFIG
DDC Bus
SMBus
DDC
V2P5
SCL VRA
SDA ZL2102 VR
SALRT
VDDS
PG
MGN
EN
VDDP
BST
CB
0.1µF
10µF
4.7µF
4.7µF
CIN
100µF
LOUT
2.2µH
SYNC
VSET
SA
FC
CFG
SS
SW
VSEN
PGND
SGND
DGND
ePAD
COUT
200µF
FIGURE 1. TYPICAL APPLICATION DIAGRAM
VIN
12V
VOUT
3.3V
6A
November 20, 2014
FN8440.2
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013, 2014. All Rights Reserved
Intersil (and design), PowerNavigator and Digital-DC are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ZL2102
Absolute Maximum Ratings
DC Supply Voltage for VDDP, VDDS Pins . . . . . . . . . . . . . . . . . . -0.3V to 17V
High-Side Supply Voltage for BST Pin. . . . . . . . . . . . . . . . . . . . -0.3V to 25V
High-Side Boost Voltage for BST, SW Pins. . . . . . . . . . . . . . . . . . -0.3V to 8V
Internal MOSFET Reference for VR Pin . . . . . . . . . . . . . . . . . . -0.3V to 8.5V
Internal Analog Reference for VRA Pin . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Internal 2.5V Reference for V2P5 Pin . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V
Logic I/O Voltage for EN, CFG, DDC, FC, MGN, PG, SDA, SCL,
SA, SALRT, SS, SYNC, VSET, VSEN Pins . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Ground Differential for DGND - SGND, PGND - SGND Pins . . . . . . . . ±0.3V
MOSFET Drive Reference Current for VR Pin Internal Bias Usage . . . 20mA
Switch Node Current for SW Pin Peak (Sink Or Source) . . . . . . . . . . . . 10A
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V
Latch-up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
36 Ld QFN Package (Notes 4, 5) . . . . . . . .
28
1.7
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Dissipation Limits (Note 6)
TA = +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5W
TA = +55°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5W
TA = +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4W
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Input Supply Voltage Range, VDDP, VDDS (see Figure 10 on page 10)
VDDS tied to VR, VRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
VDDS tied to VR, VRA Floating . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V to 7.5V
VR, VRA Floating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.5V to 14V
Output Voltage Range, VOUT (Note 7) . . . . . . . . . . . . . . . . . . . 0.54V to 5.5V
Operating Junction Temperature Range, TJ. . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the device mounted on a multi-layer FR4 test board and the exposed metal pad soldered to a low impedance ground
plane using multiple vias.
5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
6. Thermal impedance is dependent upon PCB layout.
7. Includes margin limits.
Electrical Specifications VDDP = VDDS = 12V, TA = -40°C to +85°C unless otherwise noted (Note 9). Typical values are at
TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
MIN MAX
(Note 8) TYP (Note 8) UNIT
IC INPUT AND BIAS SUPPLY CHARACTERISTICS
IDD Supply Current
IDD Shutdown Current
fSW = 200kHz, no load
fSW = 1MHz, no load
EN = 0 V, no SMBus activity, low power standby
mode
–
–
–
15 25
15 30
0.6 1
mA
mA
mA
VR Reference Output Voltage
VRA Reference Output Voltage
V2P5 Reference Output Voltage
VDD > 8V, IVR < 10mA
VDD > 5.5V, IVRA < 20mA
IV2P5 < 20mA
6.5 7.0 7.5
4.5 5.1 5.5
2.25 2.5 2.75
V
V
V
OUTPUT CHARACTERISTICS
Output Current
IRMS, continuous
Peak (Note 11)
––6
––9
A
A
Output Voltage Adjustment Range (Note 10)
Output Voltage Set-point Accuracy
VIN > VOUT
Across line, load, temperature variation
0.6 – 5.0
V
-1 – 1
%
Output Voltage Set-point Resolution
Set using PMBus command
– ±2 – mV
VSEN Input Bias Current
VSEN = 5.5V
– 110 200 µA
Submit Document Feedback
5
FN8440.2
November 20, 2014
5 Page 
ZL2102
RSA
(kΩ)
10 or LOW
11 or OPEN
12.1 or HIGH
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
28.7
31.6
34.8
38.3
TABLE 2. PIN STRAP OPTIONS
SMBus
ADDRESS
RSA
(kΩ)
20h 42.2
21h 46.4
22h 51.1
23h 56.2
24h 61.9
25h 68.1
26h 75
27h 82.5
28h 91
29h 100
2Ah 110
2Bh 121
2Ch 133
2Dh 147
2Eh 162
SMBus
ADDRESS
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
Output Voltage and VOUT_MAX Selection
(VSET)
The output voltage may be set to any voltage between 0.6V and
5.5V provided that the input voltage is higher than the desired
output voltage by an amount sufficient to prevent the device
from exceeding its maximum duty cycle specification. VOUT can
be set to any of the pin strap options shown in Table 3. VOUT can
also be set using the VOUT_COMMAND PMBus command.
The maximum accepted value of VOUT is limited by VOUT_MAX.
The default value of VOUT_MAX is 110% of the VSET pin strap
setting, but it can also be set using the VOUT_MAX PMBus
command.
RSET
(kΩ)
10
11
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
TABLE 3.
VOUT
(V)
0.6
0.7
0.75
0.8
0.9
1
1.05
1.1
1.125
1.15
RSET
(kΩ)
LOW
51.1
56.2
61.9
68.1
75
82.5
91
100
110
VOUT
(V)
1.8
1.9
2
2.1
2.2
2.4
2.5
2.6
2.7
2.8
RSET
(kΩ)
26.1
28.7
31.6
34.8
38.3
42.2
46.4
TABLE 3. (Continued)
VOUT
(V)
RSET
(kΩ)
1.2 121
1.25
133
1.3 HIGH
1.4 147
1.5 162
1.6 OPEN
1.7
VOUT
(V)
2.9
3
3.3
4
4.5
5
In addition to the VOUT_COMMAND and VOUT_MAX settings, this
pin strap setting is also used to set several other VOUT related
settings including:
• VOUT_UV_FAULT_LIMIT = 85% of VSET
• POWER_GOOD_ON = 90% of VSET
• VOUT_MARGIN_LOW = 95% of VSET
• VOUT_MARGIN_HIGH = 105% of VSET
• VOUT_OV_FAULT_LIMIT = 115% of VSET
The above parameters are automatically adjusted by the VSET
pin strap selection. If the value of VOUT_COMMAND is adjusted
via PMBus, the values of these commands may also need to be
adjusted to compensate for the VOUT change. The configured
voltage relationships must follow: VOUT_UV_FAULT_LIMIT <
POWER_GOOD_ON < VOUT_MARGIN_LOW < VOUT_COMMAND <
VOUT_MARGIN_HIGH < VOUT_OV_FAULT_LIMIT.
Automatic Loop Compensation (FC)
The ZL2102 has an automatic loop compensation feature that
measures the characteristics of the power train and calculates
the proper PID tap coefficients. Auto compensation is configured
using the FC pin as shown in Table 4.
TABLE 4.
RFC
(kΩ)
LOW
10
11
12.1
13.3
PG ASSERT
AUTO COMP GAIN
(%)
Auto Comp Disabled
After Auto Comp
100
After PG Delay
After Auto Comp
90
After PG Delay
14.7
16.2
17.8
19.6
21.5
23.7
After Auto Comp
After PG Delay
After Auto Comp
After PG Delay
After Auto Comp
After PG Delay
80
70
60
Submit Document Feedback 11
FN8440.2
November 20, 2014
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ZL2102.PDF ] | |
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