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PDF ISL89165 Data sheet ( Hoja de datos )
| Número de pieza | ISL89165 | |
| Descripción | Power MOSFET Driver | |
| Fabricantes | Intersil | |
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DATASHEET
High Speed, Dual Channel, 6A, Power MOSFET Driver
with Enable Inputs
ISL89163, ISL89164, ISL89165
The ISL89163, ISL89164, and ISL89165 are high-speed, 6A,
dual channel MOSFET drivers with enable inputs. These parts are
very similar to the ISL89160, ISL89161, ISL89162 drivers but
with an added enable input for each channel occupying NC pins 1
and 8 of the ISL89160, ISL89161, ISL89162.
Precision thresholds on all logic inputs allow the use of external
RC circuits to generate accurate and stable time delays on both
the main channel inputs, INA and INB, and the enable inputs,
ENA and ENB. The precision delays capable of these precise logic
thresholds makes these parts very useful for dead time control
and synchronous rectifiers. Note that the ENable and INput logic
inputs can be interchanged for alternate logic implementations.
Three input logic thresholds are available: 3.3V (CMOS), 5.0V
(CMOS or TTL compatible), and CMOS thresholds that are
proportional to VDD.
At high switching frequencies, these MOSFET drivers use very
little internal bias currents. Separate, non-overlapping drive
circuits are used to drive each CMOS output FET to prevent
shoot-thru currents in the output stage.
The start-up sequence is design to prevent unexpected glitches
when VDD is being turned on or turned off. When VDD < ~1V, an
internal 10kΩ resistor between the output and ground helps to
keep the output voltage low. When ~1V < VDD < UV, both outputs
are driven low with very low resistance and the logic inputs are
ignored. This insures that the driven FETs are off. When
VDD > UVLO, and after a short delay, the outputs now respond to
the logic inputs.
Features
• Dual output, 6A peak currents, can be paralleled
• Dual AND-ed input logic, (INput and ENable)
• Typical ON-resistance <1Ω
• Specified Miller plateau drive currents
• Very low thermal impedance (JC = 3°C/W)
• Hysteretic Input logic levels for 3.3V CMOS, 5V CMOS, TTL and
Logic levels proportional to VDD
• Precision threshold inputs for time delays with external RC
components
• 20ns rise and fall time driving a 10nF load.
Applications
• Synchronous Rectifier (SR) Driver
• Switch mode power supplies
• Motor Drives, Class D amplifiers, UPS, Inverters
• Pulse Transformer driver
• Clock/Line driver
Related Literature
• AN1603 “ISL6752/54EVAL1Z ZVS DC/DC Power Supply with
Synchronous Rectifiers User Guide”
ENA
INA
GND
INB
1
2
3
4
EPAD
VDD
ENB
8
7 OUTA
6
5 OUTB
4.7µF
FIGURE 1. TYPICAL APPLICATION
3.0
POSITIVE THRESHOLD LIMITS
2.5
2.0
1.5 NEGATIVE THRESHOLD LIMITS
1.0
0.5
0.0
-40 -25 -10
5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FIGURE 2. TEMP STABLE LOGIC THRESHOLDS
September 30, 2015
FN7707.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC. 2010-2012, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL89163, ISL89164, ISL89165
DC Electrical Specifications VDD = 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply
over the operating junction temperature range, -40°C to +125°C. (Continued)
PARAMETERS
INPUTS
SYMBOL
TEST CONDITIONS
TJ = +25°C
MIN TYP MAX
TJ = -40°C to +125°C
MIN
(Note 8)
MAX
(Note 8)
UNITS
Input Range
for INA, INB, ENA, ENB
VIN Option A, B, or C
- - - GND VDD V
Logic 0 Threshold
for INA, INB, ENA, ENB
(Note 11)
Option A, nominally 37% x 3.3V
VIL Option B, nominally 37% x 5.0V
Option C, nominally 20% x 12V
(Note 9)
- 1.22 -
- 1.85 -
- 2.4 -
1.12
1.70
2.00
1.32
2.00
2.76
V
V
V
Logic 1 Threshold
for INA, INB, ENA, ENB
(Note 11)
Option A, nominally 63% x 3.3V
VIH Option B, nominally 63% x 5.0V
Option C, nominally 80% x 12V
(Note 9)
- 2.08 -
- 3.15 -
- 9.6 -
1.98
3.00
9.24
2.18
3.30
9.96
V
V
V
Input Capacitance of INA, INB,
ENA, ENB (Note 10)
CIN
-2-
-
- pF
Input Bias Current
for INA, INB, ENA, ENB
IIN GND < VIN < VDD
---
-10
+10 µA
OUTPUTS
High Level Output Voltage
VOHA VOHB
- - - VDD - 0.1 VDD
V
Low Level Output Voltage
VOLA
VOLB
- - - GND GND + 0.1 V
Peak Output Source Current
IO VO (initial) = 0V, CLOAD = 10nF
- -6 -
-
-A
Peak Output Sink Current
IO VO (initial) = 12V, CLOAD = 10nF
- +6 -
-
-A
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. The nominal 20% and 80% thresholds for option C are valid for any value within the specified range of VDD.
10. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic
capacitance.
11. The true state input voltage for the non-inverted inputs is greater than the Logic 1 threshold voltage. The true state input voltage for the inverted
inputs is less than the logic 0 threshold voltage.
12. A 400µs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 9.
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5
FN7707.4
September 30, 2015
5 Page 
ISL89163, ISL89164, ISL89165
Power Dissipation of the Driver
The power dissipation of the ISL89163, ISL89164, ISL89165 is
dominated by the losses associated with the gate charge of the
driven bridge FETs and the switching frequency. The internal bias
current also contributes to the total dissipation but is usually not
significant as compared to the gate charge losses.
12
10 VDS = 64V
8 VDS = 40V
6
4
2
00 2 4 6 8 10 12 14 16 18 20 22
Qg, GATE CHARGE (nC)
FIGURE 19. MOSFET GATE CHARGE vs GATE VOLTAGE
24
Figure 19 illustrates how the gate charge varies with the gate
voltage in a typical power MOSFET. In this example, the total gate
charge for Vgs = 10V is 21.5nC when VDS = 40V. This is the
charge that a driver must source to turn-on the MOSFET and
must sink to turn-off the MOSFET.
Equation 2 shows calculating the power dissipation of the driver:
PD = 2 Qc freq VGS -R----g---a----t--e-R---+--g---ra--D-t--e-S------O-----N---- + IDDfreq VDD
(EQ. 2)
where:
freq = Switching frequency,
VGS = VDD bias of the ISL89163, ISL89164, ISL89165
Qc = Gate charge for VGS
IDD(freq) = Bias current at the switching frequency (see Figure 10)
rDS(ON) = ON-resistance of the driver
Rgate = External gate resistance (if any).
Note that the gate power dissipation is proportionally shared with
the external gate resistor. Do not overlook the power dissipated
by the external gate resistor.
Typical Application Circuits
This drive circuit provides primary to secondary line isolation. A
controller, on the primary side, is the source of the SR control
signals OUTLLN and OUTLRN signals. The secondary side signals,
V1 and V2 are rectified by the dual diode, D9, to generate the
secondary side bias for U4. V1 and V3 are also inverted by Q100
and Q101 and the rising edges are delayed by R27/C10 and
R28/C9 respectively to generate the SR drive signals, LRN and
LLN. For more complete information on this SR drive circuit, and
other applications for the ISL89163, ISL89164, ISL89165, refer
to AN1603 “ISL6752/54EVAL1Z ZVS DC/DC Power Supply with
Synchronous Rectifiers User Guide”.
PWM
L
R
L
/OUTLLN
/OUTLRN
V1
V2
LLN
V3
V4
LRN
Primary to Secondary side self
biasing, Isolated SR drive
OUTLLN
V1
D9 R27
V2
Q100
EL7212
OUTLRN
T6
V3
Red dashed lines point out the
turn-on delay of the SRs when
PWM goes low
C123
Q101
VBIAS
ENABLE
LRN
R28
V4
U4
ISL89163
U4
C9 C10
LLN
R-SR
LSR
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback 11
FN7707.4
September 30, 2015
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ISL89165.PDF ] | |
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