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PDF ISL94212 Data sheet ( Hoja de datos )
| Número de pieza | ISL94212 | |
| Descripción | Multi-Cell Li-Ion Battery Manager | |
| Fabricantes | Intersil | |
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DATASHEET
Multi-Cell Li-Ion Battery Manager
ISL94212
The ISL94212 Li-ion battery manager IC supervises up to 12
series connected cells. The part provides accurate monitoring,
cell balancing and extensive system diagnostics functions.
Three cell balancing modes are provided: Manual Balancing
mode, Timed Balancing mode and Auto Balance mode. The
Auto Balance mode terminates balancing functions when a
charge transfer value has been met.
The ISL94212 communicates to a host microcontroller via an
SPI interface and to other ISL94212 devices using a robust,
proprietary, two-wire Daisy Chain system.
The ISL94212 is offered in a 64 Ld TQFP package and is
specified for an operational temperature range of -40°C to
+85°C.
Applications
• Light electric vehicle (LEV); E-Moto; E-Bike
• Battery backup systems; Energy Storage Systems (ESS)
• Solar Farms
• Portable and semi-portable equipment
Features
• Up to 12-cell voltage monitors, support Li-Ion CoO2, Li-ion
Mn2O4, and Li-ion FePO4 chemistries
• Cell voltage measurement accuracy ±10mV
• 13-bit cell voltage measurement
• Pack voltage measurement accuracy ±180mV
• 14-bit pack voltage and temperature measurements
• Cell voltage scan rate of 19.5µs per cell (234µs to scan
12 cells)
• Internal temperature monitoring
• Up to four external temperature inputs
• Robust daisy chain communications system
• Integrated system diagnostics for all key internal functions
• Hardwired and communications based fault notification
• Integrated watchdog shuts down device if communication is
lost
• 7µA shutdown current: Enable = VSS
• 2Mbps SPI
VG1 VG1
ISL94212
DHi2
DLo2
TO OTHER DEVICES (OPTIONAL)
ISL94212
VG2 VG2
DHi2
DLo2
DHi1
DLo1
SCLK
DOUT
DIN
CS
DATA READY
FAULT
EN
HOST
MICRO
VG1
VG1
MONITOR BOARD (Master or Standalone)
VG2
MONITOR BOARD (Daisy Chain - Optional)
FIGURE 1. TYPICAL APPLICATION
April 23, 2015
FN7938.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2015. All Rights Reserved
Intersil is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL94212
Pin Descriptions
SYMBOL
PIN NUMBER
DESCRIPTION
VC0, VC1, VC2, VC3, VC4,
VC5, VC6, VC7, VC8, VC9,
VC10, VC11, VC12
20, 18, 16,
14, 12, 10, 8,
6, 4, 2, 64,
62, 60
Battery cell voltage inputs. VCn connects to the positive terminal of CELLn and the negative terminal of
CELLn+1. (VC12 connects only to the positive terminal of CELL12 and VC0 only connects with the negative
terminal of CELL1.)
CB1, CB2, CB3, CB4, CB5, 19, 17, 15, Cell Balancing FET control outputs. Each output controls an external FET which provides a current path
CB6, CB7, CB8, CB9, CB10, 13, 11, 9, 7, around the cell for balancing.
CB11, CB12
5, 3, 1, 63, 61
VBAT
58, 59 Main IC Supply pins. Connect to the most positive terminal in the battery string.
VSS 21, 22 Ground. These pins connect to the most negative terminal in the battery string.
ExT1, ExT2, ExT3, ExT4
24, 26, 28,
30
External temperature monitor or general purpose inputs. The temperature inputs are intended for use with
external resistor networks using NTC type thermistor sense elements but may also be used as general
purpose analog inputs at the user’s discretion. 0V to 2.5V input range.
TEMPREG
29 Temperature monitor voltage regulator output. This is a switched 2.5V output, which supplies a reference
voltage to external NTC thermistor circuits to provide ratiometric ADC inputs for temperature
measurement.
VDDEXT
32 External V3P3 supply input/output. Connected to the V3P3 pin via a switch, this pin may be used to power
external circuits from the V3P3 supply. The switch is open when the ISL94212 is placed in Sleep mode.
REF 33 2.5V voltage reference decoupling pin. Connect a 2.0µF to 2.5µF X7R capacitor to VSS. Do not connect any
additional external load to this pin.
VCC 34 Analog supply voltage input. Connect to V3P3 via a 33Ω resistor. Connect a 1µF capacitor to ground.
V2P5
35 Internal 2.5V digital supply decoupling pin. Connect a 1µF capacitor to DGND.
V3P3
36 3.3V digital supply voltage input. Connect the emitter of the external NPN regulator transistor to this pin.
Connect a 1µF capacitor to DGND.
Base
38 Regulator control pin. Connect the external NPN transistor’s base. Do not let this pin float,
DNC 37, 39, 48 Do not connect. Leave pins floating.
Comms Select 1
41 Communications port 1 mode select pin. Connect via a 1kΩ resistor to V3P3 for Daisy Chain
communications on port 1 or to DGND for SPI operation on port 1.
Comms Select 2
40 Communications port 2 mode select pin. Connect via a 1kΩ resistor to V3P3 to enable port 2 or to DGND
to disable this port.
Comms Rate 0,
Comms Rate 1
43, 42
Daisy Chain communications data rate setting. Connect via a 1kΩ resistor to DGND (‘0’) or to V3P3 (‘1’) to
select between various communication data rates.
DGND
44 Digital Ground.
Fault
45 Logic fault output. Asserted low if a fault condition exists.
Data Ready
46 SPI data ready. Asserted low when the device is ready to transmit data to the host microcontroller.
EN 47 Enable input. Tie to V3P3 to enable the part. Tie to DGND to disable (all IC functions are turned off).
DOUT/NC
49 Serial Data Output (SPI) or
NC (Daisy Chain). 0V to 3.3V push-pull output.
DIN/NC
50 Serial Data Input (SPI) or
NC (Daisy Chain). 0V to 3.3V input.
CS/DLo1
52 Chip-Select, active low 3.3V input (SPI) or
Daisy Chain port 1 Lo connection.
SCLK/DHi1
53 Serial-Clock Input (SPI) or
Daisy Chain port 1 Hi connection.
DHi2
56 Daisy Chain port 2 Hi connection.
DLo2
55 Daisy Chain port 2 Lo connection.
NC 23, 25, 27, No internal connection.
31, 51, 54,
57
Submit Document Feedback
5
FN7938.1
April 23, 2015
5 Page 
ISL94212
Electrical Specifications VBAT = 6 to 60V, TA = -40°C to +85°C, unless otherwise specified. Boldface limits apply across the operating
temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
MAX
TYP (Note 7) UNITS
VREF Reference Accuracy Error
VRACC
VREF value calculated using stored coefficients.
VBAT = 39.6V, VREF typical = 2.5V
(See “Voltage Reference Check Calculation” on
page 86.)
Temperature = 0°C to +50°C
-15
15 mV
Temperature = -40°C to 0°C
-40 40 mV
Temperature = +50°C to +85°C
-22 22 mV
Voltage Reference Check Timeout
tVREF
Time to check voltage reference value from power-on,
enable or wake up
20 ms
Oscillator Check Timeout
tOSC Time to check main oscillator frequency from power-on,
20
ms
enable or wake up
Oscillator Check Filter Time
CELL OPEN WIRE DETECTION
tOSCF Minimum duration of fault required for detection
100 ms
(See sections “Scan Wires” on page 22, “ISCN, PIN37, PIN39” on page 30, and “Open Wire Test” on page 45.)
Open Wire Current
Open Wire Detection Time
Open VC0 Detection Threshold
Open VC1 Detection Threshold
Primary Detection Threshold, VC2
to VC12
Secondary Detection Threshold,
VC2 to VC12
Open VBAT Fault Detection
Threshold
IOW
tOW
VVC0
VVC1
VVC2_12P
VVC2_12S
VVBO
ISCN bit = 0; VBAT = 39.6V
ISCN bit = 1; VBAT = 39.6V
Open wire current source “on” time
CELL1 negative terminal (with respect to VSS)
VBAT = 39.6V
CELL1 positive terminal (with respect to VSS)
VBAT = 39.6V
V(VC(n - 1)) - V(VCn), n = 2 to 12
VBAT = 39.6V
Via ADC. VC2 to VC12 only
VBAT = 39.6V
VC12 - VBAT
0.125
0.85
1.2
0.6
-2
-100
0.15
1.0
4.6
1.5
0.175
1.15
1.8
mA
mA
ms
V
0.7 0.8 V
-1.5 0 V
-30 50 mV
200 mV
Open VSS Fault Detection
Threshold
VVSSO VSS - VC0
250 mV
MEASUREMENT FUNCTION TIMING (Note 8)
Cell Sample Time Start
Time to sample the first cell (CELL12) following CS going
High. Scan voltages command
65 71.5 µs
Cell Sample Time Duration
Time to scan all 12 cells
(sample of CELL12 to sample of CELL1) scan voltages
command.
233 257 µs
Scan Voltages Processing Time
Time from start of scan to registers loaded to
DATA READY going low
770 847 µs
Scan Temperatures Processing
Time
Time from start of scan to registers loaded to
DATA READY going low
2690
2959
µs
Scan Mixed Processing Time
Time from start of scan to registers loaded to
DATA READY going low
830 913 µs
Scan Wires Processing Time
Time from start of scan to registers loaded to
DATA READY going low
59.4 65.3 ms
Scan All Processing Time
Time from start of scan to registers loaded to
DATA READY going low
63.2 69.5 ms
Submit Document Feedback 11
FN7938.1
April 23, 2015
11 Page | ||
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| PDF Descargar | [ Datasheet ISL94212.PDF ] | |
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