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PDF ISL97698 Data sheet ( Hoja de datos )
| Número de pieza | ISL97698 | |
| Descripción | High Efficient 2-Channel White LED Driver | |
| Fabricantes | Intersil | |
| Logotipo |  |
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High Efficient 2-Channel White LED Driver for
Smartphone Backlighting
ISL97698
The ISL97698 is a highly integrated 2-channel LED driver for
white LED (WLED) backlit TFT-LCD panels. The device is
comprised of a synchronous boost converter and two low-side
current sinks that are capable of driving an output voltage up
to 23.5V and 25mA LED current, per string. The IC operates
from an input supply of 2.5V to 5.5V.
The driver features Dynamic Headroom Control that monitors
the highest LED forward voltage string to determine the
requested boost output voltage. With a controlled low 70mV
headroom voltage and low 0.35mA IC supply current, the
device provides very high efficiency.
The ISL97698 offers 8-bit linear or 11-bit logarithmic
controlled analog output current, with dimming control from a
PWM, SWIRE, or I2C interface. Internally, the PWM duty cycle,
SWIRE, and I2C digital inputs are converted to a DC LED
current. This analog dimming scheme provides high efficiency
and eliminates audible noise and PWM dimming related EMI
concerns. The ISL97698 also features Content Adaptive
Backlight Control (CABC), which uses the product of the PWM
and SWIRE, or PWM and I2C, or SWIRE and I2C inputs to
determine the LED string current. The I2C interface is also
used for configuration settings and fault detection. The
ISL97698 incorporates various protections including: open
circuit, short circuit, and thermal shutdown.
The device is offered in a 1.39mmx 1.69mm, 3x4 array
WLCSP package. It is specified for operation over the -40°C to
+85°C ambient temperature range.
Features
• High Efficiency Operation:
- Up to 91% with 2P4S configuration
- Up to 90% with 2P6S configuration
• Extremely Low Supply Current (0.35mA)
• Dynamic Headroom Control
- Very low headroom voltage (70mV)
• 20mm2 Total Solution PCB Area
- Only three external components required
• Analog Dimming Control by PWM, SWIRE, or I2C
• 8-bit Linear or 11-bit Logarithmic Analog Output Current
Control
• Content Adaptive Backlight Control (CABC)
• Input Voltage from 2.5V to 5.5V
• 23.5V Maximum Output Voltage
• Drives 50µA to 25mA LED Strings
• Open Circuit and Short Circuit Fault Protection
• 12 Bump, 0.4mm Pitch Chip Scale Package
Applications
• WLED backlit LCD displays for Smartphones, digital
cameras, GPS, etc.
VIN
2.5V to 5.5V
CIN
L
10 µH
VIN
SCL
SDA
PWMI
SWIRE
VIN_ IO
EN
ISL 97698
LX
VOUT
VOUT
Up to 23.5V
COUT
3.3µF
GND
CH0
CH1
September 5, 2013
FN8417.0
FIGURE 1. ISL97698 TYPICAL APPLICATION CIRCUIT: TFT-LCD BACKLIGHT
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL97698
Absolute Maximum Ratings
VOUT, LX (to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 24.5V
VIN, VIN_IO, SCL, SDA, PWMI, SWIRE, EN (to GND) . . . . . . . . . . -0.3V to 6V
CH0, CH1 (to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Maximum Average Current Into LX Pin . . . . . . . . . . . . . . . . . . . . . . . . . .1.1A
ESD Rating
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 2kV
Latch Up (Tested per JESD78: Class II, Level A) . . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
12 Bump, 0.4mm Pitch CSP (Notes 4, 5) .
90
60
Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V
Digital Interface Supply Voltage (VIN_IO) . . . . . . . . . . . . . . . . . 1.8V to 5.5V
Output Voltage (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Up to 23.5V
Output Current per Channel (CH0, CH1) . . . . . . . . . . . . . . . . . . Up to 25mA
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CH0/CH1 Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379
5. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VIN = VIN_IO = EN = 3.7V, TA = +25°C unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +85°C.
PARAMETER
DESCRIPTION
CONDITION
MIN MAX
(Note 6) TYP (Note 6) UNIT
GENERAL
VIN Input Supply Voltage
2.5 5.5 V
VIN_IO Digital Interface Supply Voltage
5.5 V
IVIN
ISHUTDOWN
VINUVLO
VIN Supply Current
VIN Shutdown Supply Current
VIN Undervoltage Lockout
LX not switching (Overdrive VOUT)
EN = 0V
VIN rising
Hysteresis
0.35
13
2.2 2.3 2.4
150
mA
µA
V
mV
VIN_IOUVLO VIN_IO Undervoltage Lockout Threshold
VIN_IO rising
Hysteresis
1.4 1.5 1.6
V
70 mV
BOOST REGULATOR
TSS Soft-Start Time
If soft-start goes through all 8 steps and Boost
FET current reaches the limit
7
ms
ILX Boost FET Current Limit
IPFM
Peak FET Current in PFM Mode
rDS(ON)N Boost Low-Side Switch ON-Resistance
rDS(ON)P Boost High-Side Switch ON-Resistance
DMAX
Boost Maximum Duty Cycle
DMIN
Boost Minimum Duty Cycle
fSW Boost Switching Frequency
ILX_LEAKAGE LX Leakage Current
REFERENCE
When ABS not active (04h<4> = 0)
fSW = 850kHz
fSW = 850kHz
Default frequency setting (04h<3:0> = Ah)
LX = 23.5V
0.9 1.1 1.3
A
250 296 350 mA
300 mΩ
470 mΩ
92 %
15 %
765 850 935 kHz
10 µA
IMATCH Channel-to-Channel DC Current Matching
ILED = 1mA to 25mA
-2.5
+2.5
%
5 FN8417.0
September 5, 2013
5 Page 
ISL97698
BYTE FORMAT
Every byte transferred on SDA must be 8 bits in length. After
every byte of data sent by the transmitter there must be an
Acknowledge bit (from the receiver) to signify that the previous
8 bits were transferred successfully. Data is always transferred
on SDA with the most significant bit (MSB) first. See
“Acknowledge (ACK)”.
ACKNOWLEDGE (ACK)
Each 8-bit data transfer is followed by an Acknowledge (ACK) bit
from the receiver. The Acknowledge bit signifies that the previous
8 bits of data was transferred successfully (master-slave or
slave-master).
When the Master sends data to the Slave (e.g., during a WRITE
transaction), after the 8th bit of a data byte is transmitted, the
Master tri-states the SDA line during the 9th clock. The Slave
device acknowledges that it received all 8 bits by pulling down
the SDA line, generating an ACK bit.
When the Master receives data from the Slave (e.g. during a data
READ transaction), after the 8th bit is transmitted, the Slave
tri-states the SDA line during the 9th clock. The Master
acknowledges that it received all 8 bits by pulling down the SDA
line, generating an ACK bit.
NOT ACKNOWLEDGE (NACK)
A Not Acknowledge (NACK) is generated when the receiver does
not pull-down the SDA line during the acknowledge clock (i.e.,
SDA line remains HIGH during the 9th clock). This indicates to the
Master that it can generate a STOP condition to end the
transaction and free the bus.
A NACK can be generated for various reasons, for example:
• After an I2C device address is transmitted, there is NO receiver
with that address on the bus to respond.
• The receiver is busy performing an internal operation (e.g.,
reset, recall, etc), and cannot respond.
• The Master (acting as a receiver) needs to indicate the end of a
transfer with the Slave (acting as a transmitter).
DEVICE ADDRESS AND R/W BIT
Data transfers follow the format shown in Figure 20 and
Figure 21. After a valid START condition, the first byte sent in a
transaction contains the 7-bit Device (Slave) Address plus a
direction (R/W) bit. The Device Address identifies which device
(of up to 127 devices on the I2C bus) the Master wishes to
communicate with.
After a START condition, the ISL97698 monitors the first 8 bits
(Device Address Byte) and checks for its 7-bit Device Address in
the MSBs. If it recognizes the correct Device Address it will ACK,
and becomes ready for further communication. If it does not see
its Device Address, it will sit idle until another START condition is
issued on the bus.
To access the ISL97698, the 7-bit Device Address is 27h
(0100111x), located in MSB bits <b7:b1>. The eighth bit of the
Device Address byte (LSB bit <b0>) indicates the direction of
transfer, READ or WRITE (R/W). A “0” indicates a WRITE
operation - the Master will transmit data to the ISL97698
(receiver). A “1” indicates a Read operation - the Master will
receive data from the ISL97698 (transmitter) (see Figure 19).
B7 B6 B5 B4 B3 B2 B1
B0
0 1 0 0 1 1 1 R/W
DEVICE ADDRESS = 27h
READ = 1
WRITE = 0
FIGURE 19. DEVICE ADDRESS BYTE FORMAT
11 FN8417.0
September 5, 2013
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet ISL97698.PDF ] | |
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