PDF CY7C1399 Data sheet ( Hoja de datos )

Número de pieza	CY7C1399
Descripción	32K x 8 3.3V Static RAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY7C1399 Features • Single 3.3V power supply • Ideal for low-voltage cache memory applications • High speed — 12/15 ns • Low active power — 255 mW (max.) • Low CMOS standby power (L) — 180 µW (max.), f=fMAX • 2.0V data retention (L) — 40 µW • Low-power alpha immune 6T cell • Plastic SOJ and TSOP packaging Functional Description The CY7C1399 is a high-performance 3.3V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory expansion Logic Block Diagram A0 A1 A2 AA34 A5 A6 AA78 A9 CE WE OE INPUT BUFFER 32K x 8 ARRAY COLUMN DECODER POWER DOWN 32K x 8 3.3V Static RAM is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and three-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. An active LOW Write Enable signal (WE) controls the writing/ reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the con- tents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. The CY7C1399 is available in 28-pin standard 300-mil-wide SOJ and TSOP Type I packages. I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Pin Configurations SOJ Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 VCC 27 WE 26 A4 25 A3 24 A2 23 A1 22 OE 21 A0 20 CE 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3 C1399–2 C1399–1 Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (µA) Maximum CMOS Standby Current (µA) L 7C1399–12 12 60 500 50 7C1399–15 15 55 500 50 7C1399–20 20 50 500 50 7C1399–25 25 45 500 50 7C1399–35 35 40 500 50 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 March 25, 1999 1 page CY7C1399 Data Retention Waveform VCC 3.0V tCDR CE DATA RETENTION MODE VDR ≥ 2V Switching Waveforms Read Cycle No. 1[10, 11] ADDRESS DATA OUT tOHA PREVIOUS DATA VALID tAA tRC 3.0V tR DATA VALID C1399–5 C1399–6 Read Cycle No. 2[11, 12] CE tACE OE DATA OUT VCC SUPPLY CURRENT tDOE tLZOE HIGH IMPEDANCE tLZCE tPU 50% tRC DATA VALID tHZOE tHZCE HIGH IMPEDANCE tPD 50% ICC ISB C1399–7 Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 5 5 Page

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