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부품번호 | P2V64S40ETP 기능 |
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기능 | 64Mb Synchronous DRAM | ||
제조업체 | Deutron Electronics | ||
로고 | |||
64Mb Synchronous DRAM Specification
P2V64S40ETP
Deutron Electronics Corp.
8F, 68, SEC. 3, NANKING E. RD., TAIPEI 104,
TAIWAN, R. O. C.
TEL : 886-2-2517-7768
FAX : 886-2-2517-4575
http: // www.deutron.com.tw
64Mb Synchronous DRAM
P2V64S40ETP (4-bank x 1,048,576-word x 16-bit)
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
VIN,VOUT
VDD, VDDQ
TSTG
PD
IOS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1.0
50
Unit
V
V
°C
W
mA
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, 0 to 70°C for Commercial)
Parameter
Symbol
Min Typ
Max
Unit
Note
Supply voltage
VDD
VDDQ
3.0 3.3 3.6 V
3.0 3.3 3.6 V
Input logic high voltage
VIH 2.0
VDDQ + 0.3
V
1
Input logic low voltage
VIL -0.3 0 0.8 V 2
Output logic high voltage
VOH 2.4 -
- V IOH = -0.1mA
Output logic low voltage
VOL - - 0.4 V IOL = 0.1mA
Input leakage current
ILI
-5 -
5 uA 3
Output leakage current
IoL
-5 -
5 uA 3
Note:
1. VIH(max) = 4.6V AC for pulse width ≤ 10ns acceptable.
2. VIL(min) = -1.5V AC for pulse width ≤ 10ns acceptable.
3. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V.
4. Dout is disabled , 0V ≤ VOUT ≤ VDD.
CAPACITANCE ( Vdd =3.3V, TA = 23°C, f = 1MHz, Vref = 0.9V ± 50mV)
Parameter
Symbol
Min
Max
Unit
Clock
Cclk 2.0 4.0 pF
/CAS,/RAS,/WE,/CS,CKE,L/UDQM
Cin
2.0 4.0 pF
Address
CADD
2.0 4.0 pF
DQ0~DQ15
COUT
3.0 6.0 pF
Note
Aug. 2005
Page- 3
Rev. 1.1
4페이지 64Mb Synchronous DRAM
P2V64S40ETP (4-bank x 1,048,576-word x 16-bit)
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
-5 -6 -7
Unit
Note
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Auto refresh cycle time
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tARFC(min)
10 12 14
ns 1
15 18 21
ns 1
15 18 21
ns 1
40 42
ns 1
100 100 100
us
58 63
ns 1
22
2
CLK
2
-
1
1
1
CLK
2
1
1
1
CLK
2
60 70
ns
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
2. Minimum delay is required to complete write.
Aug. 2005
Page- 6
Rev. 1.1
7페이지 | |||
구 성 | 총 30 페이지수 | ||
다운로드 | [ P2V64S40ETP.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
P2V64S40ETP | 64Mb Synchronous DRAM | Deutron Electronics |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |