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841N4830 데이터시트 PDF




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부품번호 841N4830 기능
기능 NG Crystal-To-HCSL Frequency Synthesizer
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841N4830 데이터시트, 핀배열, 회로
FemtoClock® NG Crystal-To-HCSL
Frequency Synthesizer
841N4830
DATA SHEET
General Description
The 841N4830 is a 3 HCSL, 1 LVPECL and 2 LVCMOS output
Synthesizer optimized to generate PCI Express reference clock
frequencies. The device uses IDT’s fourth generation FemtoClock®
NG technology for synthesis of high clock frequency at very low
phase noise. It provides low power consumption with good power
supply noise rejection. Using a 25MHz, 12pF parallel resonant
crystal, the following frequencies can be generated: 100MHz,
50MHz and 25MHz. Maximum rms phase jitter of 0.36ps, easily
meets PCI Express jitter requirements. The 841N4830 is packaged
in a small 32-pin VFQFN package.
Features
Fourth generation FemtoClock® Next Generation (NG) technology
Three differential HCSL outputs, one differential LVPECL and
two single-ended LVCMOS/LVTTL outputs
Crystal oscillator interface designed for a 25MHz, 12pF parallel
resonant crystal
CLK/nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
A 25MHz crystal generates output frequencies of: 100MHz,
50MHz and 25MHz
VCO frequency: 2GHz
RMS Phase Jitter @ 100MHz, (12kHz – 20MHz) using a 25MHz
crystal: 0.36ps (maximum)
Power supply noise rejection PSNR: -45dB (typical)
PCI Express Gen 2 (5 Gb/s) jitter compliant
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
nOE_REF Pulldown
PLL_BYPASS Pulldown
nOEA Pulldown
XTAL_IN
XTAL_OUT
CLK Pulldown
nCLK Pullup
CLK_SEL Pullup
25MHz
OSC
0
1
IREF
DIV2_QB Pullup
nOEB Pulldown
PFD
&
LPF
FemtoClock® NG
VCO
2GHz
1
÷20
0
÷1 0
÷80 ÷2 1
Pin Assignment
25MHz LVPECL
REF_OUT
nREF_OUT
100MHz HCSL
3QA[2:0]
3
nQA[2:0]
100MHz LVCMOS
QA3
32 31 30 29 28 27 26 25
PLL_BYPASS 1
24 QA1
nOE_REF 2
841N4830
23 nQA1
nOEB 3
32-Lead VFQFN
22 VDDO
DIV2_QB 4 5mm x 5mm x 0.925mm 21 QA2
VDDA 5
package body
20 nQA2
CLK 6
nCLK 7
K Package
Top View
19 GND
18 QA3
VDDO_REF 8
17 VDDO_QA3
9 10 11 12 13 14 15 16
100/50MHz
LVCMOS
QB
841N4830 Rev E 7/1/15
1 ©2015 Integrated Device Technology, Inc.




841N4830 pdf, 반도체, 판매, 대치품
841N4830 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics
or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, VDD
Inputs, VI
Outputs, VO (LVCMOS, HCSL)
Rating
3.63V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
Outputs, IO (LVPECL)
Continuos Current
Surge Current
Package Thermal Impedance, JA
Storage Temperature, TSTG
50mA
100mA
37.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDD_OSC = 3.0V to 3.6V, VDDO = VDDO_QA3 = VDDO_QB = VDDO_REF =
2.7V to 3.6V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD,
VDD_OSC
Core Supply Voltage
VDDA
Analog Supply Voltage
VDDO,
VDDOx
Output Supply Voltage
IEE Power Supply Current
IDDA
Analog Supply Current
Included in IEE
3.0
VDD – 0.32
2.7
3.3
3.3
3.3
3.6 V
VDD
V
3.6 V
170 mA
32 mA
VDDOx denotes VDDO_REF, VDDO_QA3 and VDDO_QB.
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.0V to 3.6V, VDDO_QA3 = VDDO_QB = 2.7V to 3.6V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH Input High Voltage
VIL Input Low Voltage
CLK_SEL,
DIV2_QB
IIH
Input
High Current
nOEA, nOEB,
nOE_REF,
PLL_BYPASS
VDD = VIN = 3.6V
VDD = VIN = 3.6V
2
-0.3
VDD + 0.3
0.8
5
V
V
µA
150 µA
CLK_SEL,
DIV2_QB
IIL
Input
Low Current
nOEA, nOEB,
nOE_REF,
PLL_BYPASS
VDD = 3.6V, VIN = 0V
VDD = 3.6V, VIN = 0V
-150
-5
µA
µA
FEMTOCLOCK® NG CRYSTAL-TO-HCSL FREQUENCY SYNTHESIZER
4
Rev E 7/1/15

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841N4830 전자부품, 판매, 대치품
841N4830 DATA SHEET
Table 6C. HCSL AC Characteristics, VDD = 3.0V to 3.6V, VDDO = 2.7V to 3.6V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
fOUT
Output Frequency
PLL
PLL Bypass
100
20
fREF
tsk(b)
Reference Frequency
Bank Skew; NOTE 1, 10
25
tjit(Ø)
Phase Jitter, RMS (Random); 100MHz, Integration Range:
NOTE 11
12kHz – 20MHz
tREFCLK_HF_RMS Phase Jitter RMS; NOTE 2
100MHz, 25MHz crystal input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
0.600
tREFCLK_LF_RMS Phase Jitter RMS; NOTE 2
100MHz, 25MHz crystal input
Low Band: 10kHz - 1.5MHz
0.023
tjit(cc)
Cycle-to-Cycle Jitter
PLL Mode
tL PLL Lock Time
VRB
Ring-back Voltage Margin;
NOTE 4, 9
-100
tSTABLE
Time before VRB is allowed;
NOTE 4, 9
500
VHIGH
VLOW
VCROSS
Voltage High
Voltage Low
Absolute Crossing Voltage;
NOTE 3, 6, 7
520
-150
160
VCROSS
Total Variation of VCROSS
over all edges; NOTE 3, 6, 8
Rising Edge Rate; NOTE 4, 5
0.6
Falling Edge Rate; NOTE 4, 5
0.6
PSNR
Power Supply Noise
Reduction
-45
odc Output Duty Cycle; NOTE 4
49
Maximum
50
0.36
Units
MHz
MHz
MHz
ps
ps
ps
ps
30 ps
10 ms
100 mV
ps
920 mV
150 mV
460 mV
140 mV
4.0 V/ns
4.0 V/ns
dB
51 %
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also
the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
NOTE 3: Measurement taken from single ended waveform.
NOTE 4: Measurement taken from differential waveform.
NOTE 5: Measured from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic through
the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 6: Measured at the crosspoint where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.
NOTE 7: Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all crosspoints
for this measurement.
NOTE 8: Defined as the total variation of all crossing voltages of rising Q and falling nQ, This is the maximum allowed variance in VCROSS for
any particular system.
NOTE 9: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100mV differential range.
NOTE 10: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 11: See Phase Noise Plot.
Rev E 7/1/15
7 FEMTOCLOCK® NG CRYSTAL-TO-HCSL FREQUENCY SYNTHESIZER

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부품번호상세설명 및 기능제조사
841N4830

NG Crystal-To-HCSL Frequency Synthesizer

Integrated Device Technology
Integrated Device Technology

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