8T49N241 PDF 데이터시트 ( Data ) - Integrated Device Technology

부품번호

8T49N241 기능

기능

NG Universal Frequency Translator

제조업체

Integrated Device Technology

로고

8T49N241 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.

전체 30 페이지

미리보기를 사용할 수 없습니다

FemtoClock® NG Universal Frequency

Translator

8T49N241

Datasheet

General Description

The 8T49N241 has one fractional-feedback PLL that can be used as

a jitter attenuator and frequency translator. It is equipped with one

integer and three fractional output dividers, allowing the generation

of up to four different output frequencies, ranging from 8kHz to 1GHz.

These frequencies are completely independent of each other, the

input reference frequencies and the crystal reference frequency. The

device places virtually no constraints on input to output frequency

conversion, supporting all FEC rates, including the new revision of

ITU-T Recommendation G.709 (2009), most with 0ppm conversion

error. The outputs may select among LVPECL, LVDS, HCSL or

LVCMOS output levels.

This makes it ideal to be used in any frequency synthesis application,

including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and

SONET/SDH, including ITU-T G.709 (2009) FEC rates.

The 8T49N241 accepts up to two differential or single-ended input

clocks and a fundamental-mode crystal input. The internal PLL can

lock to either of the input reference clocks or just to the crystal to

behave as a frequency synthesizer. The PLL can use the second

input for redundant backup of the primary input reference, but in this

case, both input clock references must be related in frequency.

The device supports hitless reference switching between input

clocks. The device monitors both input clocks for Loss of Signal

(LOS), and generates an alarm when an input clock failure is

detected. Automatic and manual hitless reference switching options

are supported. LOS behavior can be set to support gapped or

un-gapped clocks.

The 8T49N241 supports holdover. The holdover has an initial

accuracy of ±50ppB from the point where the loss of all applicable

input reference(s) has been detected. It maintains a historical

average operating point for the PLL that may be returned to in

holdover at a limited phase slope.

The PLL has a register-selectable loop bandwidth from 0.2Hz to

6.4kHz.

The device supports Output Enable & Clock Select inputs and Lock,

Holdover & LOS status outputs.

The device is programmable through an I2C interface. It also

supports I2C master capability to allow the register configuration to

be read from an external EEPROM.

Programming with IDT’s Timing Commander software is

recommended for optimal device performance. Factory

pre-programmed devices are also available.

Applications

• OTN or SONET / SDH equipment

• Gigabit and Terabit IP switches / routers including Synchronous

Ethernet

• Video broadcast

Features

• Supports SDH/SONET and Synchronous Ethernet clocks including

all FEC rate conversions

• 0.35ps RMS Typical Jitter (including spurs): 12kHz to 20MHz

• Operating Modes: Synthesizer, Jitter Attenuator

• Operates from a 10MHz to 50MHz fundamental-mode crystal or a

10MHz to 125MHz external oscillator

• Initial holdover accuracy of +50ppb.

• Accepts up to 2 LVPECL, LVDS, LVHSTL or LVCMOS input clocks

• Accepts frequencies ranging from 8kHz to 875MHz

• Auto and manual clock selection with hitless switching

• Clock input monitoring including support for gapped clocks

• Phase-slope limiting and fully hitless switching options to control

output clock phase transients

• Generates four LVPECL / LVDS / HCSL or eight LVCMOS output

clocks

• Output frequencies ranging from 8kHz up to 1.0GHz

(differential)

• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)

• One integer divider ranging from ÷4 to ÷786,420

• Three fractional output dividers (see Section, “Output Dividers”)

• Programmable loop bandwidth settings from 0.2Hz to 6.4kHz

• Optional fast-lock function

• Four General Purpose I/O pins with optional support for status &

control:

• Two Output Enable control inputs provide control over the four

clocks

• Manual clock selection control input

• Lock, Holdover and Loss-of-Signal alarm outputs

• Open-drain Interrupt pin

• Register programmable through I2C or via external I2C EEPROM

• Full 2.5V or 3.3V supply modes, 1.8V support for LVCMOS outputs,

GPIO and control pins

• -40°C to 85°C ambient operating temperature

• Package: 40QFN, lead-free (RoHS 6)

REVISION 6, October 31, 2016

8T49N241 Datasheet

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

Number

Name

Type1

Description

VCCA

Power

VCCA

Power

Analog function supply for core analog functions. 2.5V or 3.3V supported.

Analog function supply for analog functions associated with the PLL. 2.5V or 3.3V

supported.

3 GPIO[0] I/O Pullup General-purpose input-output. LVTTL / LVCMOS Input levels.

VCCO0

Power

High-speed output supply for output pair Q0, nQ0. 2.5V or 3.3V supported for

differential output types. LVCMOS outputs also support 1.8V.

5 Q0 O Universal Output Clock 0. Please refer to the Section, “Output Drivers” for more details.

6 nQ0 O Universal Output Clock 0. Please refer to the Section, “Output Drivers” for more details.

7 GPIO[1] I/O Pullup General-purpose input-output. LVTTL / LVCMOS Input levels.

8 nQ1 O Universal Output Clock 1. Please refer to the Section, “Output Drivers” for more details.

9 Q1 O Universal Output Clock 1. Please refer to the Section, “Output Drivers” for more details.

VCCO1

Power

High-speed output supply for output pair Q1, nQ1. 2.5V or 3.3V supported for

differential output types. LVCMOS outputs also support 1.8V.

SDATA

I/O Pullup I2C interface bi-directional data.

SCLK

I/O Pullup I2C interface bi-directional clock.

13 VCC Power

14 VEE Power

Core digital function supply. 2.5V or 3.3V supported.

Negative supply voltage. All VEE pins and EPAD must be connected before any

positive supply voltage is applied.

15 VCC Power

Core digital function supply. 2.5V or 3.3V supported.

16 CLK0 I Pulldown Non-inverting differential clock input 0.

Pullup / Inverting differential clock input 0.

17 nCLK0 I

Pulldown VCC / 2 when left floating (set by internal pullup / pulldown resistors)

18 CLK1 I Pulldown Non-inverting differential clock input 1.

19 nCLK1 I Pullup / Inverting differential clock input 1.

Pulldown VCC / 2 when left floating (set by internal pullup / pulldown resistors).

20 S_A1 I Pulldown I2C Address Bit A1

VCCO2

Power

High-speed output supply voltage for output pair Q2, nQ2. 2.5V or 3.3V

supported for differential output types. LVCMOS outputs also support 1.8V.

22 Q2 O Universal Output Clock 2. Please refer to the Section, “Output Drivers” for more details.

23 nQ2 O Universal Output Clock 2. Please refer to the Section, “Output Drivers” for more details.

24 GPIO[2] I/O Pullup General-purpose input-output. LVTTL / LVCMOS Input levels.

25 nQ3 O Universal Output Clock 3. Please refer to the Section, “Output Drivers” for more details.

26 Q3 O Universal Output Clock 3. Please refer to the Section, “Output Drivers” for more details.

VCCO3

Power

High-speed output supply voltage for output pair Q3, nQ3. 2.5V or 3.3V

supported for differential output types. LVCMOS outputs also support 1.8V.

28 GPIO[3] I/O Pullup General-purpose input-output. LVTTL / LVCMOS Input levels.

Open-drain

nINT

O with pullup Interrupt output.

Revision 6, October 31, 2016

4페이지

8T49N241 Datasheet

Principles of Operation

The 8T49N241 can be locked to either of the input clocks and

generate a wide range of synchronized output clocks.

It could be used for example in either the transmit or receive path of

Synchronous Ethernet equipment.

The 8T49N241 accepts up to two differential or single-ended input

clocks ranging from 8kHz up to 875MHz. It generates up to four

output clocks ranging from 8kHz up to 1.0GHz.

The PLL path within the 8T49N241 supports three states: Lock,

Holdover and Free-run. Lock & holdover status may be monitored on

hitless reference switching. In the locked state, the PLL locks to a

valid clock input and its output clocks have a frequency accuracy

equal to the frequency accuracy of the input clock. In the Holdover

state, the PLL will output a clock which is based on the selected

holdover behavior. The PLL within the 8T49N241 has an initial

holdover frequency offset of ±50ppb. In the Free-run state, the PLL

outputs a clock with the same frequency accuracy as the external

crystal.

Upon power up, the PLL will enter Free-run state, in this state it

generates output clocks with the same frequency accuracy as the

external crystal. The 8T49N241 continuously monitors each input for

activity (signal transitions). If no input references are provided, the

device will remain locked to the crystal in Free-run state and will

generate output frequencies as a synthesizer.

When an input clock has been validated the PLL will transition to the

Lock state. In automatic reference switching, if the selected input

clock fails and there are no other valid input clocks, the PLL will

quickly detect that and go into Holdover. In the Holdover state, the

PLL will output a clock which is based on the selected holdover

behavior. If the selected input clock fails and another input clock is

available then the 8T49N241 will hitlessly switch to that input clock.

The reference switch can be either revertive or non-revertive. Manual

switchover is also available with switchover only occurring on user

command, either via register bit or via the Clock Select input function

of the GPIO[3:0] pins.

The device supports conversion of any input frequencies to four

different independent output frequencies.

The 8T49N241 has a programmable loop bandwidth from 0.2Hz to

6.4kHz.

The device monitors all input clocks and generates an alarm when an

input clock failure is detected.

The device is programmable through an I2C and may also

autonomously read its register settings from an internal One-Time

Programmable (OTP) memory or an external serial I2C EEPROM.

Crystal Input

The crystal input on the 8T49N241 is capable of being driven by a

parallel-resonant, fundamental mode crystal with a frequency range

of 10MHz – 50MHz.

The oscillator input also supports being driven by a single-ended

crystal oscillator or reference clock.

The initial holdover frequency offset is set by the device, but the long

term drift depends on the quality of the crystal or oscillator attached

to this port.

This device provides the ability to double the crystal frequency input

into the PLL for improved close-in phase noise performance. Refer to

Figure 3.

To Q[2:3] Bypass Path

OSC

x2 0

To Analog PLL

Figure 3. Doubler Block Diagram

Bypass Path

The crystal input, CLK0 or CLK1 may be used directly as a clock

source for the Q[2:3] output dividers. This may only be done for input

frequencies of 250MHz or less.

Input Clock Selection

The 8T49N241 accepts up to two input clocks with frequencies

ranging from 8kHz up to 875MHz. Each input can accept LVPECL,

LVDS, LVHSTL, HCSL or LVCMOS inputs using 1.8V, 2.5V or 3.3V

logic levels.

In Manual mode, only one of the inputs may be chosen and if that

input fails that PLL will enter holdover.

Manual mode may be operated by directly selecting the desired input

reference in the REFSEL register field. It may also operate via

pin-selection of the desired input clock by selecting that mode in the

REFSEL register field. In that case, GPIO[2] must be used as a Clock

Select input (CSEL). CSEL = 0 will select the CLK0 input and CSEL

= 1 will select the CLK1 input.

In addition, the crystal frequency may be passed directly to the output

dividers Q[2:3] for use as a reference.

Revision 6, October 31, 2016

7페이지

구 성

총 30 페이지

다운로드

[ 8T49N241.PDF 데이터시트 ]

Integrated Device Technology에서 제조한 전자 부품 8T49N241은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.

8T49N241의 기능 및 특징 중 하나는 "NG Universal Frequency Translator" 입니다.

일반적으로, Integrated Device Technology에서 제조되는 전자부품들은 우수한 성능과
품질에 대한 신뢰성을 갖추고 있습니다.

구매 문의

일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ]

PDF 형식의 8T49N241 데이터시트 제공 ( 특징, 기능 )

관련 데이터시트

부품번호	상세설명 및 기능	제조사
8T49N241	NG Universal Frequency Translator	Integrated Device Technology
8T49N242	NG Universal Frequency Translator	Integrated Device Technology