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8T49N242 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8T49N242
기능 NG Universal Frequency Translator
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8T49N242 데이터시트, 핀배열, 회로
FemtoClock® NG Universal Frequency
Translator
8T49N242
Datasheet
General Description
The 8T49N242 has one fractional-feedback PLL that can be used as
a jitter attenuator and frequency translator. It is equipped with four
integer output dividers, allowing the generation of up to four different
output frequencies, ranging from 8kHz to 1GHz. These frequencies
are completely independent of the input reference frequencies and
the crystal reference frequency. The device places virtually no
constraints on input to output frequency conversion, supporting all
FEC rates, including the new revision of ITU-T Recommendation
G.709 (2009), most with 0ppm conversion error. The outputs may
select among LVPECL, LVDS, HCSL or LVCMOS output levels.
This makes it ideal to be used in any frequency synthesis application,
including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and
SONET/SDH, including ITU-T G.709 (2009) FEC rates.
The 8T49N242 accepts up to two differential or single-ended input
clocks and a fundamental-mode crystal input. The internal PLL can
lock to either of the input reference clocks or just to the crystal to
behave as a frequency synthesizer. The PLL can use the second
input for redundant backup of the primary input reference, but in this
case, both input clock references must be related in frequency.
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS), and generates an alarm when an input clock failure is
detected. Automatic and manual hitless reference switching options
are supported. LOS behavior can be set to support gapped or
un-gapped clocks.
The 8T49N242 supports holdover. The holdover has an initial
accuracy of ±50ppB from the point where the loss of all applicable
input reference(s) has been detected. It maintains a historical
average operating point for the PLL that may be returned to in
holdover at a limited phase slope.
The PLL has a register-selectable loop bandwidth from 0.2Hz to
6.4kHz.
The device supports Output Enable & Clock Select inputs and Lock,
Holdover & LOS status outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Programming with IDT’s Timing Commander software is
recommended for optimal device performance. Factory
pre-programmed devices are also available.
Applications
• OTN or SONET / SDH equipment
• Gigabit and Terabit IP switches / routers including Synchronous
Ethernet
• Video broadcast
Features
• Supports SDH/SONET and Synchronous Ethernet clocks including
all FEC rate conversions
• 0.35ps RMS Typical Jitter (including spurs): 12kHz to 20MHz
• Operating Modes: Synthesizer, Jitter Attenuator
• Operates from a 10MHz to 50MHz fundamental-mode crystal or a
10MHz to 125MHz external oscillator
• Initial holdover accuracy of +50ppb.
• Accepts up to 2 LVPECL, LVDS, LVHSTL or LVCMOS input clocks
• Accepts frequencies ranging from 8kHz to 875MHz
• Auto and manual clock selection with hitless switching
• Clock input monitoring including support for gapped clocks
• Phase-slope limiting and fully hitless switching options to control
output clock phase transients
• Generates four LVPECL / LVDS / HCSL or eight LVCMOS output
clocks
• Output frequencies ranging from 8kHz up to 1.0GHz
(differential)
• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
• Integer divider ranging from ÷4 to ÷786,420 for each output
• Programmable loop bandwidth settings from 0.2Hz to 6.4kHz
• Optional fast-lock function
• Four General Purpose I/O pins with optional support for status &
control:
• Two Output Enable control inputs provide control over the four
clocks
• Manual clock selection control input
• Lock, Holdover and Loss-of-Signal alarm outputs
• Open-drain Interrupt pin
• Register programmable through I2C or via external I2C EEPROM
• Full 2.5V or 3.3V supply modes, 1.8V support for LVCMOS outputs,
GPIO and control pins
• -40°C to 85°C ambient operating temperature
• Package: 40QFN, lead-free (RoHS 6)
©2016 Integrated Device Technology, Inc.
1
REVISION 6, November 1, 2016




8T49N242 pdf, 반도체, 판매, 대치품
8T49N242 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
1 VCCA
2 VCCA
3 GPIO[0]
4 VCCO0
5 Q0
6 nQ0
7 GPIO[1]
8 nQ1
9 Q1
10 VCCO1
11 SDATA
12 SCLK
13 VCC
14 VEE
15 VCC
16 CLK0
17 nCLK0
18 CLK1
19 nCLK1
20 S_A1
21 VCCO2
22 Q2
23 nQ2
24 GPIO[2]
25 nQ3
26 Q3
27 VCCO3
28 GPIO[3]
29 nINT
30 VCCA
31 nRST
Type1
Description
Power
Analog function supply for core analog functions. 2.5V or 3.3V supported.
Power
Analog function supply for analog functions associated with the PLL. 2.5V or
3.3V supported.
I/O Pullup General-purpose input-output. LVTTL / LVCMOS Input levels.
Power
High-speed output supply for output pair Q0, nQ0. 2.5V or 3.3V supported for
differential output types. LVCMOS outputs also support 1.8V.
O Universal Output Clock 0. Please refer to the Section, “Output Drivers” for more details.
O Universal Output Clock 0. Please refer to the Section, “Output Drivers” for more details.
I/O Pullup General-purpose input-output. LVTTL / LVCMOS Input levels.
O Universal Output Clock 1. Please refer to the Section, “Output Drivers” for more details.
O Universal Output Clock 1. Please refer to the Section, “Output Drivers” for more details.
Power
I/O
I/O
Pullup
Pullup
High-speed output supply for output pair Q1, nQ1. 2.5V or 3.3V supported for
differential output types. LVCMOS outputs also support 1.8V.
I2C interface bi-directional data.
I2C interface bi-directional clock.
Power
Core digital function supply. 2.5V or 3.3V supported.
Power
Negative supply voltage. All VEE pins and EPAD must be connected before any
positive supply voltage is applied.
Power
Core digital function supply. 2.5V or 3.3V supported.
I Pulldown Non-inverting differential clock input 0.
Pullup / Inverting differential clock input 0.
I
Pulldown VCC / 2 when left floating (set by internal pullup / pulldown resistors)
I Pulldown Non-inverting differential clock input 1.
Pullup / Inverting differential clock input 1.
I
Pulldown VCC / 2 when left floating (set by internal pullup / pulldown resistors).
I Pulldown I2C Address Bit A1
Power
High-speed output supply voltage for output pair Q2, nQ2. 2.5V or 3.3V
supported for differential output types. LVCMOS outputs also support 1.8V.
O Universal Output Clock 2. Please refer to the Section, “Output Drivers” for more details.
O Universal Output Clock 2. Please refer to the Section, “Output Drivers” for more details.
I/O Pullup General-purpose input-output. LVTTL / LVCMOS Input levels.
O Universal Output Clock 3. Please refer to the Section, “Output Drivers” for more details.
O Universal Output Clock 3. Please refer to the Section, “Output Drivers” for more details.
Power
High-speed output supply voltage for output pair Q3, nQ3. 2.5V or 3.3V
supported for differential output types. LVCMOS outputs also support 1.8V.
I/O Pullup General-purpose input-output. LVTTL / LVCMOS Input levels.
O Open-drain Interrupt output.
with pullup
Power
Analog function supply for analog functions associated with PLL. 2.5V or 3.3V
supported.
Master Reset input. LVTTL / LVCMOS interface levels:
I
Pullup
0 = All registers and state machines are reset to their default values
1 = Device runs normally
©2016 Integrated Device Technology, Inc.
4
Revision 6, November 1, 2016

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8T49N242 전자부품, 판매, 대치품
8T49N242 Datasheet
Inputs do not support transmission of spread-spectrum clocking
sources. Since this family is intended for high-performance
applications, it will assume input reference sources to have stabilities
of +100ppm or better, except where gapped clock inputs are used.
If the PLL is working in automatic mode, then one of the input
reference sources is assigned as the higher priority. At power-up or
if the currently selected input reference fails, the PLL will switch to the
highest priority input reference that is valid at that time (see Section,
“Input Clock Monitor” for details).
Automatic mode has two sub-options: revertive or non-revertive. In
revertive mode, the PLL will switch to a reference with a higher
priority setting whenever one becomes valid. In non-revertive mode
the PLL remains with the currently selected source as long as it
remains valid.
The clock input selection is based on the input clock priority set by
the Clock Input Priority control bit.
Input Clock Monitor
Each clock input is monitored for Loss of Signal (LOS). If no activity
has been detected on the clock input within a user-selectable time
period then the clock input is considered to be failed and an internal
Loss-of-Signal status flag is set, which may cause an input
switchover depending on other settings. The user-selectable time
period has sufficient range to allow a gapped clock missing many
consecutive edges to be considered a valid input.
User-selection of the clock monitor time-period is based on a counter
driven by a monitor clock. The monitor clock is fixed at the frequency
of the PLL’s VCO divided by 8. With a VCO range of 3GHz - 4GHz,
the monitor clock has a frequency range of 375MHz to 500MHz.
The monitor logic for each input reference will count the number of
monitor clock edges indicated in the appropriate Monitor Control
register. If an edge is received on the input reference being
monitored, then the count resets and begins again. If the target edge
count is reached before an input reference edge is received, then an
internal soft alarm is raised and the count re-starts. During the soft
alarm period, the PLL tracking will not be adjusted. If an input
reference edge is received before the count expires for the second
time, then the soft alarm status is cleared and the PLL will resume
adjustments. If the count expires again without any input reference
edge being received, then a Loss-of-Signal alarm is declared.
It is expected that for normal (non-gapped) clock operation, users will
set the monitor clock count for each input reference to be slightly
longer than the nominal period of that input reference. A margin of
2-3 monitor clock periods should give a reasonably quick reaction
time and yet prevent false alarms.
For gapped clock operation, the user will set the monitor clock count
to a few monitor clock periods longer than the longest expected clock
gap period. The monitor count registers support 17-bit count values,
which will support at least a gap length of two clock periods for any
supported input reference frequency, with longer gaps being
supported for faster input reference frequencies. Since gapped
clocks usually occur on input reference frequencies above 100MHz,
gap lengths of thousands of periods can be supported.
Using this configuration for a gapped clock, the PLL will continue to
adjust while the normally expected gap is present, but will freeze
once the expected gap length has been exceeded and alarm after
twice the normal gap length has passed.
Once a LOS on any of the input clocks is detected, the appropriate
internal LOS alarm will be asserted and it will remain asserted until
that input clock returns and is validated. Validation occurs once 8
rising edges have been received on that input reference. If another
error condition on the same input clock is detected during the
validation time then the alarm remains asserted and the validation
period starts over.
Each LOS flag may also be reflected on one of the GPIO[3:0]
outputs. Changes in status of any reference can also generate an
interrupt if not masked.
Holdover
The 8T49N242 supports a small initial holdover frequency offset in
non-gapped clock mode. When the input clock monitor is set to
support gapped clock operation, this initial holdover frequency offset
is indeterminate since the desired behavior with gapped clocks is for
the PLL to continue to adjust itself even if clock edges are missing. In
gapped clock mode, the PLL will not enter holdover until the input is
missing for two LOS monitor periods.
The holdover performance characteristics of a clock are referred as
its accuracy and stability, and are characterized in terms of the
fractional frequency offset. The 8T49N242 can only control the initial
frequency accuracy. Longer-term accuracy and stability are
determined by the accuracy and stability of the external oscillator.
When the PLL loses all valid input references, it will enter the
holdover state. In fast average mode, the PLL will initially maintain its
most recent frequency offset setting and then transition at a rate
dictated by its selected phase-slope limit setting to a frequency offset
setting that is based on historical settings. This behavior is intended
to compensate for any frequency drift that may have occurred on the
input reference before it was detected to be lost.
The historical holdover value will have three options:
• Return to center of tuning range within the VCO band
• Instantaneous mode - the holdover frequency will use the DPLL
current frequency 100msec before it entered holdover. The
accuracy is shown in the AC Characteristics Table, Table 11.
• Fast average mode - an internal IIR (Infinite Impulse Response)
filter is employed to get the frequency offset. The IIR filter gives a
3dB attenuation point corresponding to nominal a period of 20
minutes. The accuracy is shown in the AC Characteristics Table,
Table 11.
©2016 Integrated Device Technology, Inc.
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부품번호상세설명 및 기능제조사
8T49N241

NG Universal Frequency Translator

Integrated Device Technology
Integrated Device Technology
8T49N242

NG Universal Frequency Translator

Integrated Device Technology
Integrated Device Technology

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