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부품번호 8T49N286
기능 NG Octal Universal Frequency Translator
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8T49N286 데이터시트, 핀배열, 회로
FemtoClock® NG Octal Universal
Frequency Translator
8T49N286
Datasheet
General Description
The 8T49N286 has two independent, fractional-feedback PLLs that
can be used as jitter attenuators and frequency translators. It is
equipped with six integer and two fractional output dividers, allowing
the generation of up to eight different output frequencies, ranging
from 8kHz to 1GHz. Four of these frequencies are completely
independent of each other and the inputs. The other four are related
frequencies. The eight outputs may select among LVPECL, LVDS,
HCSL or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency
translation application, including 1G, 10G, 40G and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates. The device may also behave as a frequency
synthesizer.
The 8T49N286 accepts up to four differential or single-ended input
clocks and a crystal input. Each of the two internal PLLs can lock to
different input clocks which may be of independent frequencies. The
other two input clocks are intended for redundant backup of the
primary clocks and must be related in frequency to their primary.
The device supports hitless reference switching between input
clocks. The device monitors all input clocks for Loss of Signal (LOS),
and generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are
supported. LOS behavior can be set to support gapped or un-gapped
clocks.
The 8T49N286 supports holdover for each PLL. The holdover has an
initial accuracy of ±50ppB from the point where the loss of all
applicable input reference(s) has been detected. It maintains a
historical average operating point for each PLL that may be returned
to in holdover at a limited phase slope.
The device places no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error.
Each PLL has a register-selectable loop bandwidth from 1.4Hz to
360Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I2C interface. It also supports
I2C master capability to allow the register configuration to be read
from an external EEPROM. The user may select whether the
programming interface uses I2C protocols or SPI protocols, however
in SPI mode, read from the external EEPROM is not supported.
Applications
OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
OTN de-mapping (Gapped Clock and DCO mode)
Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
SyncE (G.8262) applications
Wireless base station baseband
Data communications
100G Ethernet
Features
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
<0.3ps RMS Typical Jitter (including spurs), 12kHz to 20MHz
Operating modes: locked to input signal, holdover and free-run
Initial holdover accuracy of ±50ppb
Accepts up to four LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
Accepts frequencies ranging from 8kHz up to 875MHz
Auto and manual input clock selection with hitless switching
Clock input monitoring, including support for gapped clocks
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
Operates from a 10MHz to 40MHz fundamental-mode crystal
Generates 8 LVPECL / LVDS / HCSL or 16 LVCMOS output
clocks
Output frequencies ranging from 8kHz up to 1.0GHz (diff)
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
Eight General Purpose I/O pins with optional support for status
and control
Eight Output Enable control inputs
Lock, Holdover and Loss-of-Signal status outputs
Open-drain Interrupt pin
Write-protect pin to prevent configuration registers being altered
Nine programmable loop bandwidth settings for each PLL from
1.4Hz to 360Hz.
Optional Fast Lock function
Programmable output phase delays in steps as small as 16ps
Register programmable through I2C / SPI or via external I2C
EEPROM
Bypass clock paths for system tests
Power supply modes:
VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
-40°C to 85°C ambient operating temperature
Package: 72QFN, lead-free RoHs (6)
©2016 Integrated Device Technology, Inc.
1
Revision 7, October 27, 2016




8T49N286 pdf, 반도체, 판매, 대치품
8T49N286 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
2
3
5
16
17
18
32
7
8
9
10
11
12
13
14
63, 62
57, 56
34, 35
28, 29
51, 50
47, 46
43, 42
39, 38
60
Name
OSCI
OSCO
S_A0 / nCS
SDATA / SDO
SCLK / SCLK
S_A1 / SDI
nI2C_SPI
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
nRST
Type
Description
I
Crystal Input. Accepts a 10MHz - 40MHz reference from a clock oscillator or
a 12pF fundamental mode, parallel-resonant crystal.
O
Crystal Output. This pin should be connected to a crystal. If an oscillator is
connected to OSCI, then this pin must be left unconnected.
I Pulldown I2C lower address bit A0 / SPI interface chip select signal.
I/O Pullup I2C interface bi-directional Data / SPI interface serial data output signal.
I/O Pullup I2C interface bi-directional Clock / SPI interface clock input signal.
I Pulldown I2C lower address bit A1 / SPI interface serial data input signal.
Serial Interface Mode Selection. LVCMOS Input Levels:
I Pulldown 0 = I2C Mode
1 = SPI Mode
I Pulldown Non-inverting differential clock input.
I
Pullup/ Inverting differential clock input. VCC/2 when left floating (set by the internal
Pulldown pullup and pulldown resistors.)
I Pulldown Non-inverting differential clock input.
I
Pullup/ Inverting differential clock input. VCC/2 when left floating (set by the internal
Pulldown pullup and pulldown resistors.)
I Pulldown Non-inverting differential clock input.
I
Pullup/ Inverting differential clock input. VCC/2 when left floating (set by the internal
Pulldown pullup and pulldown resistors.)
I Pulldown Non-inverting differential clock input.
I
Pullup/ Inverting differential clock input. VCC/2 when left floating (set by the internal
Pulldown pullup and pulldown resistors.)
O Universal Output Clock 0. Please refer to the Output Drivers section for more details.
O Universal Output Clock 1. Please refer to the Output Drivers section for more details.
O Universal Output Clock 2. Please refer to the Output Drivers section for more details.
O Universal Output Clock 3. Please refer to the Output Drivers section for more details.
O Universal Output Clock 4. Please refer to the Output Drivers section for more details.
O Universal Output Clock 5. Please refer to the Output Drivers section for more details.
O Universal Output Clock 6. Please refer to the Output Drivers section for more details.
O Universal Output Clock 7. Please refer to the Output Drivers section for more details.
Master Reset input. LVTTL / LVCMOS interface levels.
I Pullup 0 = All registers and state machines are reset to their default values
1 = Device runs normally
65 nINT
59 nWP
41, 45, 49, 53,
37, 54, 26, 31
69
GPIO[7:0]
PLL_BYP
O
Open-drain
with pullup
Interrupt output.
Write protect input. LVTTL / LVCMOS interface levels:
I
Pullup
0 = Write operations on the serial port will complete normally, but will have
no effect except on interrupt registers
1 = Serial port writes may change any register
I/O
Pullup
General-purpose input-outputs. LVTTL / LVCMOS Input levels Open-drain
output.Pulled-up with 5.1kresistor to VCC.
I
Pulldown
Bypass Selection. Allow input references to bypass both PLLs.
LVTTL / LVCMOS interface levels.
©2016 Integrated Device Technology, Inc.
4
Revision 7, October 27, 2016

4페이지










8T49N286 전자부품, 판매, 대치품
8T49N286 Datasheet
Principles of Operation
The 8T49N286 has two PLLs that can each independently be locked
to any of the input clocks and generate a wide range of synchronized
output clocks.
It incorporates two completely independent PLLs. These could be
used for example in the transmit and receive path of Synchronous
Ethernet equipment. Any of the input clocks can be selected as the
reference for either PLL. From the output of the two PLLs a wide
range of output frequencies can be simultaneously generated.
The 8T49N286 accepts up to four differential input clocks ranging
from 8kHz up to 875MHz. It generates up to eight output clocks
ranging from 8kHz up to 1.0GHz.
Each PLL path within the 8T49N286 supports three states: Lock,
Holdover and Free-run. Lock & holdover status may be monitored on
register bits and pins. Each PLL also supports automatic and manual
hitless reference switching. In the locked state, the PLL locks to a
valid clock input and its output clocks have a frequency accuracy
equal to the frequency accuracy of the input clock. In the Holdover
state, the PLL will output a clock which is based on the selected
holdover behavior. Each of the PLL paths within the 8T49N286 has
an initial holdover frequency offset of ±50ppb. In the Free-run state,
the PLL outputs a clock with the same frequency accuracy as the
external crystal.
Upon power up, each PLL will enter Free-run state, in this state it
generates output clocks with the same frequency accuracy as the
external crystal. The 8T49N286 continuously monitors each input for
activity (signal transitions).
In automatic reference switching, when an input clock has been
validated the PLL will transition to the locked state. If the selected
input clock fails and there are no other valid input clocks, the PLL will
quickly detect that and go into holdover. In the Holdover state, the
PLL will output a clock which is based on the selected holdover
behavior. If the selected input clock fails and another input clock is
available then the 8T49N286 will hitlessly switch to that input clock.
The reference switch can be either revertive or non-revertive.
The device supports conversion of any input frequency to four
different, independent output frequencies on the Q[0:3] outputs.
Additionally, a further four output frequencies may be generated that
are integer-related to the four independent frequencies. These
additional four frequencies are on the Q[4:7] outputs.
The 8T49N286 has a programmable loop bandwidth from 1.4Hz to
360Hz.
The device monitors all input clocks and generates an alarm when an
input clock failure is detected.
The device supports programmable individual output phase
adjustments in order to allow control of input to output phase
adjustments and output to output phase alignment.
The device is programmable through an I2C or SPI interface and may
also autonomously read its register settings from an internal
One-Time Programmable (OTP) memory or an external serial I2C
EEPROM.
Bypass Path
For system test purposes, each of PLL0 and PLL1 may be bypassed.
When PLL_BYP is asserted the CLK0 input reference will be
presented to the Q4 dividers. The CLK1 input reference will be
presented to the Q5 dividers.
Additionally, CLK0, CLK1 or CLK2 may be used as a clock source for
the output dividers of Q[4:7]. This may only be done for input
frequencies of 250MHz or less.
Input Clock Selection
The 8T49N286 accepts up to four input clocks with frequencies
ranging from 8kHz up to 875MHz. Each input can accept LVPECL,
LVDS, LVHSTL, HCSL or LVCMOS inputs using 1.8V, 2.5V or 3.3V
logic levels. To use LVCMOS inputs, please refer to the Application
Note, Wiring the Differential Input to Accept Single-Ended Levels for
biasing instructions.
The device has independent input clock selection control for each
PLL. In Manual mode, only one of these inputs may be chosen per
PLL and if that input fails that PLL will enter holdover.
Manual mode may be operated by directly selecting the desired input
reference in the REFSEL register field. It may also operate via
pin-selection of the desired input clock by selecting that mode in the
REFSEL register field. In that case, GPIOs must be used as Clock
Select inputs (CSELn[1:0]) for PLLn.
CSELn[1]
0
0
1
1
CSELn[0]
0
1
0
1
Selected Input Reference
CLK0
CLK1
CLK2
CLK3
In addition, the crystal frequency may be passed directly to the output
dividers for Q[4:7] for use as a reference.
Inputs do not support transmission of spread-spectrum clocking
sources. Since this family is intended for high-performance
applications, it will assume input reference sources to have stabilities
of +100ppm or better.
If the PLL is working in automatic mode, then each of the input
reference sources is assigned a priority of 1-4. At power-up or if the
currently selected input reference fails, the PLL will switch to the
highest priority input reference that is valid at that time (see section,
Input Clock Monitor for details).
Automatic mode has two sub-options: revertive or non-revertive. In
revertive mode, the PLL will switch to a reference with a higher
priority setting whenever one becomes valid. In non-revertive mode
the PLL remains with the currently selected source as long as it
remains valid.
The clock input selection is based on the input clock priority set by
the Clock Input Priority control registers. It is recommended that all
input references for a PLL be given different priority settings in the
Clock Input Priority control registers for that PLL.
©2016 Integrated Device Technology, Inc.
7
Revision 7, October 27, 2016

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