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8T49N287 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8T49N287
기능 NG Octal Universal Frequency Translator
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8T49N287 데이터시트, 핀배열, 회로
FemtoClock® NG Octal Universal
Frequency Translator
8T49N287
Datasheet
General Description
The 8T49N287 has two independent, fractional-feedback PLLs that
can be used as jitter attenuators and frequency translators. It is
equipped with six integer and two fractional output dividers, allowing
the generation of up to 8 different output frequencies, ranging from
8kHz to 1GHz. Four of these frequencies are completely
independent of each other and the inputs. The other four are related
frequencies. The eight outputs may select among LVPECL, LVDS,
HCSL or LVCMOS output levels.
This makes it ideal to be used in any frequency translation
application, including 1G, 10G, 40G and 100G Synchronous
Ethernet, OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC
rates. The device may also behave as a frequency synthesizer.
The 8T49N287 accepts up to two differential or single-ended input
clocks and a crystal input. Each of the two internal PLLs can lock to
different input clocks which may be of independent frequencies. Each
PLL can use the other input for redundant backup of the primary
clock, but in this case, both input clocks must be related in frequency.
The device supports hitless reference switching between input clocks.
The device monitors all input clocks for Loss of Signal (LOS), and
generates an alarm when an input clock failure is detected. Automatic
and manual hitless reference switching options are supported. LOS
behavior can be set to support gapped or un-gapped clocks.
The 8T49N287 supports holdover for each PLL. The holdover has an
initial accuracy of ±50ppB from the point where the loss of all
applicable input reference(s) has been detected. It maintains a
historical average operating point for each PLL that may be returned
to in holdover at a limited phase slope.
The device places no constraints on input to output frequency conver-
sion, supporting all FEC rates, including the new revision of ITU-T
Recommendation G.709 (2009), most with 0ppm conversion error.
Each PLL has a register-selectable loop bandwidth from 1.4Hz to
360Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Applications
OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
OTN de-mapping (Gapped Clock and DCO mode)
Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
SyncE (G.8262) applications
Wireless base station baseband
Data communications
100G Ethernet
Features
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
<0.3ps RMS Typical jitter (including spurs), 12kHz to 20MHz
Operating modes: locked to input signal, holdover and free-run
Initial holdover accuracy of ±50ppb
Accepts up to two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
Accepts frequencies ranging from 8kHz up to 875MHz
Auto and manual input clock selection with hitless switching
Clock input monitoring, including support for gapped clocks
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
Operates from a 10MHz to 40MHz fundamental-mode crystal
Generates 8 LVPECL / LVDS / HCSL or 16 LVCMOS output
clocks
Output frequencies ranging from 8kHz up to 1.0GHz (diff)
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
Four General Purpose I/O pins with optional support for status &
control:
Four Output Enable control inputs may be mapped to any of the
eight outputs
Lock, Holdover & Loss-of-Signal status outputs
Open-drain Interrupt pin
Nine programmable loop bandwidth settings for each PLL from
1.4Hz to 360Hz.
Optional Fast Lock function
Programmable output phase delays in steps as small as 16ps
Register programmable through I2C or via external I2C EEPROM
Bypass clock paths for system tests
Power supply modes
VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
-40°C to 85°C ambient operating temperature
Package: 56QFN, lead-free (RoHS 6)
©2016 Integrated Device Technology, Inc.
1
Revision 7, October 27, 2016




8T49N287 pdf, 반도체, 판매, 대치품
8T49N287 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
3
4
5
12
13
7
8
9
10
48, 47
44, 43
27, 28
23, 24
40, 39
37, 36
34, 33
31, 30
OSCI
OSCO
S_A0
SDATA
SCLK
CLK0
nCLK0
CLK1
nCLK1
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
I
Crystal Input. Accepts a 10MHz-40MHz reference from a clock oscillator or a
12pF fundamental mode, parallel-resonant crystal.
O
Crystal Output. This pin should be connected to a crystal. If an oscillator is
connected to OSCI, then this pin must be left unconnected.
I Pulldown I2C lower address bit A0.
I/O Pullup I2C interface bi-directional Data.
I/O Pullup I2C interface bi-directional Clock.
I Pulldown Non-inverting differential clock input.
I
Pullup / Inverting differential clock input. VCC/2 when left floating (set by the internal
Pulldown pullup and pulldown resistors.)
I Pulldown Non-inverting differential clock input.
I
Pullup / Inverting differential clock input. VCC/2 when left floating (set by the internal
Pulldown pullup and pulldown resistors.)
O Universal Output Clock 0. Please refer to the Output Drivers section for more details.
O Universal Output Clock 1. Please refer to the Output Drivers section for more details.
O Universal Output Clock 2. Please refer to the Output Drivers section for more details.
O Universal Output Clock 3. Please refer to the Output Drivers section for more details.
O Universal Output Clock 4. Please refer to the Output Drivers section for more details.
O Universal Output Clock 5. Please refer to the Output Drivers section for more details.
O Universal Output Clock 6. Please refer to the Output Drivers section for more details.
O Universal Output Clock 7. Please refer to the Output Drivers section for more details.
Master Reset input. LVTTL / LVCMOS interface levels:
46 nRST I Pullup 0 = All registers and state machines are reset to their default values
1 = Device runs normally
50
nINT
O
Open-drain
with pullup
Interrupt output.
29, 42, 21, 25 GPIO[3:0]
54 PLL_BYP
6, ePad
11
17
2
14, 15, 16, 20
1, 51, 55, 56
49
45
26
22
VEE
VCC
VCC
VCCA
VCCA
VCCA
VCCO0
VCCO1
VCCO2
VCCO3
I/O
I
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Pullup
Pulldown
General-purpose input-outputs. LVTTL / LVCMOS Input levels Open-drain
output.Pulled-up with 5.1kresistor to VCC.
Bypass Selection. Allow input references to bypass both PLLs.
LVTTL / LVCMOS interface levels.
Negative supply voltage. All VEE pins and EPAD must be connected before any
positive supply voltage is applied.
Core and digital functions supply voltage.
Core and digital functions supply voltage.
Analog functions supply voltage for core analog functions.
Analog functions supply voltage for analog functions associated with PLL1.
Analog functions supply voltage for analog functions associated with PLL0.
High-speed output supply voltage for output pair Q0, nQ0.
High-speed output supply voltage for output pair Q1, nQ1.
High-speed output supply voltage for output pair Q2, nQ2.
High-speed output supply voltage for output pair Q3, nQ3.
©2016 Integrated Device Technology, Inc.
4
Revision 7, October 27, 2016

4페이지










8T49N287 전자부품, 판매, 대치품
8T49N287 Datasheet
Input Clock Monitor
Each clock input is monitored for Loss of Signal (LOS). If no activity
has been detected on the clock input within a user-selectable time
period then the clock input is considered to be failed and an internal
Loss-of-Signal status flag is set, which may cause an input
switchover depending on other settings. The user-selectable time
period has sufficient range to allow a gapped clock missing many
consecutive edges to be considered a valid input.
User-selection of the clock monitor time-period is based on a counter
driven by a monitor clock. The monitor clock is fixed at the frequency
of PLL0’s VCO divided by 8. With a VCO range of 3GHz - 4GHz, the
monitor clock has a frequency range of 375MHz to 500MHz.
The monitor logic for each input reference will count the number of
monitor clock edges indicated in the appropriate Monitor Control
register. If an edge is received on the input reference being
monitored, then the count resets and begins again. If the target edge
count is reached before an input reference edge is received, then an
internal soft alarm is raised and the count re-starts. During the soft
alarm period, the PLL(s) tracking this input will not be adjusted. If an
input reference edge is received before the count expires for the
second time, then the soft alarm status is cleared and the PLL(s) will
resume adjustments. If the count expires again without any input
reference edge being received, then a Loss-of-Signal alarm is
declared.
It is expected that for normal (non-gapped) clock operation, users will
set the monitor clock count for each input reference to be slightly
longer than the nominal period of that input reference. A margin of
2-3 monitor clock periods should give a reasonably quick reaction
time and yet prevent false alarms.
For gapped clock operation, the user will set the monitor clock count
to a few monitor clock periods longer than the longest expected clock
gap period. The monitor count registers support 17-bit count values,
which will support at least a gap length of two clock periods for any
supported input reference frequency, with longer gaps being
supported for faster input reference frequencies. Since gapped
clocks usually occur on input reference frequencies above 100MHz,
gap lengths of thousands of periods can be supported.
Using this configuration for a gapped clock, the PLL will continue to
adjust while the normally expected gap is present, but will freeze
once the expected gap length has been exceeded and alarm after
twice the normal gap length has passed.
Once a LOS on any of the input clocks is detected, the appropriate
internal LOS alarm will be asserted and it will remain asserted until
that input clock returns and will be validated by the receipt of 8 rising
clock edges on that input reference. If another error condition on the
same input clock is detected during the validation time then the alarm
remains asserted and the validation time starts over.
Each LOS flag may also be reflected on one of the GPIO[3:0]
outputs. Changes in status of any reference can also generate an
interrupt if not masked.
Holdover
8T49N287 supports a small initial holdover frequency offset for each
PLL path in non-gapped clock mode. When the input clock monitor is
set to support gapped clock operation, this initial holdover frequency
offset is indeterminate since the desired behavior with gapped clocks
is for the PLL to continue to adjust itself even if clock edges are
missing. In gapped clock mode, the PLL will not enter holdover until
the input is missing for two LOS monitor periods.
The holdover performance characteristics of a clock are referred as
its accuracy and stability, and are characterized in terms of the
fractional frequency offset. The 8T49N287 can only control the initial
frequency accuracy. Longer-term accuracy and stability are
determined by the accuracy and stability of the external oscillator.
When a PLL loses all valid input references, it will enter the holdover
state. In non-gapped clock mode, the PLL will initially maintain its
most recent frequency offset setting and then transition at a rate
dictated by its selected phase-slope limit setting to a frequency offset
setting that is based on historical settings.
This behavior is intended to compensate for any frequency drift that
may have occurred on the input reference before it was detected to
be lost.
The historical holdover value will have three options:
• Return to center of tuning range within the VCO band.
• Instantaneous mode - the holdover frequency will use the
DPLL current frequency 100msec before it entered
holdover. The accuracy is shown in the AC Electrical
Characteristics, Table 11A.
• Fast average mode - an internal IIR (Infinite Impulse
Response) filter is employed to get the frequency offset.
The IIR filter gives a 3 dB attenuation point corresponding
to a nominal period of 20 minutes. The accuracy is shown
in the AC Electrical Characteristics, Table 11A.
When entering holdover, each PLL will set a separate internal HOLD
alarm internally. This alarm may be read from internal status register,
appear on the appropriate GPIO pin and/or assert the nINT output.
While a PLL is in holdover, its frequency offset is now relative to the
crystal input and so the output clocks derived from that PLL will be
tracing their accuracy to the local oscillator or crystal. At some point
in time, depending on the stability & accuracy of that source, the
clock(s) derived from that PLL will have drifted outside of the limits of
the holdover state and the system will be considered to be in a
free-run state. Since this borderline is defined outside the PLL and
dictated by the accuracy and stability of the external local crystal or
oscillator, the 8T49N287 cannot know or influence when that
transition occurs. As a result, the 8T49N287 will remain in the
holdover state internally.
©2016 Integrated Device Technology, Inc.
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Revision 7, October 27, 2016

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