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부품번호 8T49N488
기능 NG QUAD Universal Frequency Translator
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8T49N488 데이터시트, 핀배열, 회로
FemtoClock® NG QUAD Universal
Frequency Translator
8T49N488
DATA SHEET
General Description
The 8T49N488 is a quad PLL with FemtoClock® NG technology, it
integrates low phase noise Frequency Translator / Synthesizer, Jitter
attenuation, and with alarm and monitoring functions suitable for
networking and communications applications. The device has four
fully independent PLLs, each PLL is able to generate any output
frequency in the 0.98MHz - 312.5MHz range and most output
frequencies in the 312.5MHz - 1,300MHz range (see Table 3 for
details). A wide range of input reference clocks and operation
reference clock may be used as the source for the output frequency.
Each PLL of 8T49N488 has three operating modes to support a very
broad spectrum of applications:
1) Frequency Synthesizer
Synthesizes output frequencies from an external reference
clock REFCLK.
Fractional feedback division is used, so there are no
requirements for any specific input reference clock frequency to
produce the desired output frequency with a high degree of
accuracy.
2) High-Bandwidth Frequency Translator
Applications: PCI Express, Computing, General Purpose
Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation.
3) Low-Bandwidth Frequency Translator
Applications: Networking & Communications.
Translates any input clock in the 8kHz -710MHz frequency
range into any supported output frequency.
This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external REFCLK to provide
significant jitter attenuation.
Each PLL provides factory-programmed default power-up
configuration burned into One-Time Programmable (OTP) memory.
The configuration is specified by customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I2C interface and the
device can be completely reconfigured.
Features
Fourth generation FemtoClock® NG technology
Four fully independent PLLs
Universal Frequency TranslatorTM/Frequency Synthesizer and
Jitter attenuator
Outputs are programmable as LVPECL or LVDS
Programmable output frequency: 0.98MHz up to 1,300MHz
Two differential inputs support the following input levels:
LVPECL, LVDS, LVHSTL, HCSL
Input frequency range: 8kHz ~ 710MHz Low-Bandwidth
Input frequency range: 16MHz ~ 710MHz High-Bandwidth
REFCLK frequency range: 16MHz ~ 40MHz
Input clock monitor and alarm
Smoothed reference switch
Factory-set register configuration for power-up default state
Power-up default configuration
Configuration customized via One-Time Programmable ROM
Settings may be overwritten after power-up via I2C
I2C Serial interface for register programming
RMS phase jitter at 161.1328125MHz,using 40MHz REFCLK
(12kHz ~ 20MHz): 465fs (typical), Low Bandwidth Mode (FracN)
RMS phase jitter at 400MHz,using 40MHz REFCLK
(12kHz ~ 20MHz): 333fs (typical), Synthesizer Mode (Integer FB)
Full 2.5V ±5% supply mode
-40°C to 85°C ambient operating temperature
10mm X 10mm CABGA package
Lead-free (RoHS 6) packaging
8T49N488 REVISION B 03/23/15
1 ©2015 Integrated Device Technology, Inc.




8T49N488 pdf, 반도체, 판매, 대치품
8T49N488 DATA SHEET
Table 1. Pin Descriptions
Number
Name
E8 LOCKC
H5 LOCKD
D4 CLK_SELA
D6 CLK_SELB
F6 CLK_SELC
F4 CLK_SELD
E6
PLL_BYPAS
S
G6
G5
C1
C4
B5
A7
D5
D7
E7
G9
F5
E3
J3
F3
A3, B2, B3
A8, B8, C9
H8, H9, J7
G1, H2, J2
SDATA
SCLK
VCCA_A
VCCO_A
VCC_A
VCCA_B
VCCO_B
VCC_B
VCCA_C
VCCO_C
VCC_C
VCCA_D
VCCO_D
VCC_D
VEE_A
VEE_B
VEE_C
VEE_D
Type
Output
Output
Input
Pulldown
Input
Pulldown
Input
Pulldown
Input
Pulldown
Input
I/O
Input
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Pulldown
Pullup
Pullup
Description
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
Input clock select. Selects the active differential clock input.
0 = CLK0A, nCLK0A (default)
1 = CLK1A, nCLK1A
Input clock select. Selects the active differential clock input.
0 = CLK0B, nCLK0B (default)
1 = CLK1B, nCLK1B
Input clock select. Selects the active differential clock input.
0 = CLK0C, nCLK0C (default)
1 = CLK1C, nCLK1C
Input clock select. Selects the active differential clock input.
0 = CLK0D, nCLK0D (default)
1 = CLK1D, nCLK1D
Bypasses the VCXO PLL.
0 = PLL Mode (default)
1 = PLL Bypassed
I2C Data Input/Output. Open drain.
I2C Clock Input. LVCMOS/LVTTL interface levels.
Analog power supply for PLLA
Output power supply for PLLA
Core power supply for PLLA
Analog power supply for PLLB
Output power supply for PLLB
Core power supply for PLLB
Analog power supply for PLLC
Output power supply for PLLC
Core power supply for PLLC
Analog power supply for PLLD
Output power supply for PLLD
Core power supply for PLLD
Negative supply for PLLA
Negative supply for PLLB
Negative supply for PLLC
Negative supply for PLLD
REVISION B 03/23/15
4 FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR

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8T49N488 전자부품, 판매, 대치품
8T49N488 DATA SHEET
Frequency Synthesizer Mode
This mode of operation allows an arbitrary output frequency to be
generated from external REFCLK input. For improved phase noise
performance, the REFCLK input frequency is doubled. As can be
seen from the block diagram in Figure 1, only the upper feedback
loop is used in this mode of operation. It is recommended that CLK0
and CLK1 be left unused in this mode of operation.
The upper feedback loop supports a delta-sigma fractional feedback
divider. This allows the VCO operating frequency to be a non-integer
multiple of the REFCLK frequency. By using an integer multiple only,
lower phase noise jitter on the output can be achieved, however the
use of the delta-sigma divider logic will provide excellent
performance on the output if a fractional divisor is used.
The input reference frequency range is now extended up to 710MHz.
A pre-divider stage P is needed to keep the operating frequencies at
the phase detector within limits.
Low-Bandwidth Frequency Translator Mode
As can be seen from the block diagram in Figure 3, this mode
involves two PLL loops. The lower loop with the large integer dividers
is the low bandwidth loop and it sets the output-to-input frequency
translation ratio.This loop drives the upper DCXO loop (digitally
controlled crystal oscillator) via an analog-digital converter.
Figure 1. Frequency Synthesizer Mode Block Diagram
High-Bandwidth Frequency Translator Mode
This mode of operation is used to translate one of two input clocks of
the same nominal frequency into an output frequency. As can be
seen from the block diagram in Figure 2, similarly to the Frequency
Synthesizer mode, only the upper feedback loop is used.
Figure 2. High Bandwidth Frequency Translator Mode
Block Diagram
Figure 3. Low Bandwidth Frequency Translator Mode
Block Diagram
The phase detector of the lower loop is designed to work with
frequencies in the 8kHz - 16kHz range. The pre-divider stage is used
to scale down the input frequency by an integer value to achieve a
frequency in this range. By dividing down the fed-back VCO
operating frequency by the integer divider M1[18:0] to as close as
possible to the same frequency, exact output frequency translations
can be achieved.
Alarm Conditions & Status Bits
Each PLL of 8T49N488 monitors a number of conditions and reports
their status via both output pins and/or register bits. All alarms will
behave as indicated below in all modes of operation, but some of the
conditions monitored have no valid meaning in some operating
modes. For example, the status of CLK0BAD, CLK1BAD and
CLK_ACTIVE are not relevant in Frequency Synthesizer mode. The
outputs will still be active and it is left to the user to determine which
to monitor and how to respond to them based on the known operating
mode.
CLK_ACTIVE - indicates which input clock reference is being used to
derive the output frequency.
LOCK - This status is asserted on the pin & register bit when the PLL
is locked to the appropriate input reference for the chosen mode of
operation. The status bit will not assert until frequency lock has been
achieved, but will de-assert once lock is lost.
REVISION B 03/23/15
7 FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR

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