PDF ZL30250 Data sheet ( Hoja de datos )

Número de pieza	ZL30250
Descripción	3-Output Any-to-Any Clock Multiplier and Frequency Synthesizer ICs
Fabricantes	Microsemi
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Register Map: Section 6.2 Features  Four Input Clocks  One crystal/CMOS input  Two differential/CMOS inputs  One single-ended/CMOS input  Any input frequency from 9.72MHz to 1250MHz (9.72MHz to 300MHz for CMOS)  Clock selection by pin or register control  Low-Jitter Fractional-N APLL and 3 Outputs  Any output frequency from <1Hz to 1035MHz  High-resolution fractional frequency conversion with 0ppm error  Easy-to-configure, encapsulated design requires no external VCXO or loop filter components  Each output has independent dividers  Output jitter as low as 0.16ps RMS (12kHz- 20MHz integration band)  Outputs are CML or 2xCMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL  In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz)  Per-output supply pin with CMOS output voltages from 1.5V to 3.3V ZL30250, ZL30251 4-Input, 3-Output Any-to-Any Clock Multiplier and Frequency Synthesizer ICs Data Sheet March 2015 Ordering Information ZL30250LDG1 ZL30250LDF1 ZL30251LDG1 ZL30251LDF1 32 Pin QFN 32 Pin QFN 32 Pin QFN 32 Pin QFN Trays Tape and Reel Trays Tape and Reel Matte Tin Package size: 5 x 5 mm -40C to +85C  Precise output alignment circuitry and per- output phase adjustment  Per-output enable/disable and glitchless start/stop (stop high or low)  General Features  Automatic self-configuration at power-up from external (ZL30250) or internal (ZL30251) EEPROM; up to four configs, pin-selectable  SPI or I2C processor Interface  Numerically controlled oscillator mode  Spread-spectrum modulation mode  Tiny 5x5mm QFN package  Easy-to-use evaluation software Applications  Frequency conversion and frequency synthesis in a wide variety of equipment types IC1P, IC1N HSDIV1 APLL HSDIV1 DIV1 IC2P, IC2N HSDIV2 ~3.7 to 4.2GHz, IC3P/GPIO3 XA xtal HSDIV3 NCO SS Fractional-N Figure 6 HSDIV2 DIV2 DIV3 XB driver ×2 Microprocessor Port (SPI or I2C Serial) and HW Control and Status Pins OC1P, OC1N VDDO1 OC2P, OC2N VDDO2 OC3P, OC3N VDDO3 Figure 1 - Functional Block Diagram 1 Microsemi Confidential Copyright 2015. Microsemi Corporation. All Rights Reserved. 1 page 1. Application Examples ZL30250, ZL30251 50MHz ZL3025x 2x 156.25MHz differential 125MHz CMOS 25MHz CMOS Frequency synthesis from crystal resonator Figure 2 - Ethernet Frequency Synthesis Application Data Sheet 25MHz ZL3025x 3x 100MHz differential Frequency multiplication from input clock signal Figure 3 - PCI Express Frequency Multiplication Application 2. Detailed Features 2.1 Input Clock Features  Four input clocks: one crystal/CMOS, two differential/CMOS, one single-ended/CMOS  Input clocks can be any frequency from 9.72MHz up to 1250MHz (differential) or 300MHz (CMOS) 2.2 APLL Features  Very high-resolution fractional (i.e. non-integer) multiplication  Any-to-any frequency conversion with 0ppm error  Two high-speed dividers (integers 4 to 15, half divides 4.5 to 7.5)  Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter components  Bypass mode supports system testing 2.3 Output Clock Features  Three low-jitter output clocks  Each output can be one differential output or two CMOS outputs  Output clocks can be any frequency from 1Hz to 1035MHz (250MHz max for CMOS and HSTL outputs)  Output jitter as low as 0.16ps RMS (12kHz to 20MHz integration band)  In CMOS mode, an additional divider allows the OCxN pin to be an integer divisor of the OCxP pin (example: OC3P 125MHz, OC3N 25MHz)  Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL and CMOS components  Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN  Can produce clock frequencies for microprocessors, ASICs, FPGAs and other components  Can produce PCIe clocks (PCIe gen. 1, 2 and 3)  Sophisticated output-to-output phase alignment  Per-output phase adjustment with high resolution and unlimited range  Per-output enable/disable  Per-output glitchless start/stop (stop high or low) 2.4 General Features  SPI or I2C serial microprocessor interface  Automatic self-configuration at power-up from external (ZL30250) or internal (ZL30251) EEPROM memory; pin control to specify one of four stored configurations 5 Microsemi Confidential 5 Page ZL30250, ZL30251 Data Sheet terminated and must have very short trace length. A poorly terminated single-ended signal can greatly increase output jitter, and long single-ended trace lengths are more susceptible to noise. When MCR1.XAB=10, XA is enabled as a single-ended input. While the stability of the external oscillator can be important, its absolute frequency accuracy is less important because any known frequency inaccuracy of the oscillator can be compensated. When the device is configured for NCO or spread-spectrum operation, the DFREQZ parameter can be used to compensate for oscillator frequency error. When the device is configured for APLL-only mode, the APLL's fractional feedback divider value (AFBDIV) can be adjusted by ppb or ppm to compensate for oscillator frequency error. The jitter on output clock signals depends on the phase noise and frequency of the external oscillator. For the device to operate with the lowest possible output jitter, the external oscillator should have the following characteristics:  Phase Jitter: less than 0.1ps RMS over the 12kHz to 5MHz integration band  Frequency: The higher the better, all else being equal 5.3.2 External Crystal and On-Chip Driver Circuit The on-chip crystal driver circuit is designed to work with a fundamental mode, AT-cut crystal resonator. See Table 2 for recommended crystal specifications. To enable the crystal driver, set MCR1.XAB=01. See Figure 5 for the crystal equivalent circuit and the recommended external capacitor connections. To achieve a crystal load (CL) of 10pF, an external 16pF is placed in parallel with the 4pF internal capacitance of the XA pin, and an external 16pF is placed in parallel with the 4pF internal capacitance of the XB pin. The crystal then sees a load of 20pF in series with 20pF, which is 10pF total load. Note that the 16pF capacitance values in Figure 5 include all capacitance on those nodes. If, for example, PCB trace capacitance between crystal pin and IC pin is 2pF then 14pF capacitors should be used to make 16pF total. The crystal, traces, and two external capacitors should be placed on the board as close as possible to the XA and XB pins to reduce crosstalk of active signals into the oscillator. Also no active signals should be routed under the crystal circuitry. Note: Crystals have temperature sensitivies that can cause frequency changes in response to ambient temperature changes. In applications where significant temperature changes are expected near the crystal, it is recommended that the crystal be covered with a thermal cap, or an external XO or TCXO should be used instead. XTAL CO RS LS CS C1 Crystal (CL = 10pF) C2 R1 1M R2 4pF XA XB 4pF The optimal values of C1, C2 and R2 depend on PCB capacitance and crystal frequency and power rating. See application note ZLAN-494 for calculations. Figure 5 - Crystal Equivalent Circuit / Recommended Crystal Circuit Table 2 - Crystal Selection Parameters Parameter Crystal oscillation frequency1 Shunt capacitance Load capacitance Equivalent series resistance fOSC < 40MHz Symbol fOSC CO CL RS Min. 25 Typ. 2 10 Max. 60 5 60 Units MHz pF pF  11 Microsemi Confidential 11 Page

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