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부품번호 XC18V512 기능
기능 In-System Programmable Configuration PROMs
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XC18V512 데이터시트, 핀배열, 회로
— PRODUCT OBSOLETE / UNDER OBSOLESCENCE —
25
R
XC18V00 Series In-System-Programmable
Configuration PROMs
DS026 (v6.0) August 5, 2015
0
Features
In-System Programmable 3.3V PROMs for
Configuration of Xilinx FPGAs
Endurance of 20,000 Program/Erase Cycles
Program/Erase Over Full Industrial Voltage and
Temperature Range (–40°C to +85°C)
IEEE Std 1149.1 Boundary-Scan (JTAG) Support
JTAG Command Initiation of Standard FPGA
Configuration
Simple Interface to the FPGA
Cascadable for Storing Longer or Multiple Bitstreams
Product Specification
Low-Power Advanced CMOS FLASH Process
Dual Configuration Modes
Serial Slow/Fast Configuration (up to 33 MHz)
Parallel (up to 264 Mb/s at 33 MHz)
5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals
3.3V or 2.5V Output Capability
Design Support Using the Xilinx ISE™ Foundation™
Software Packages
Available in PC20, SO20, PC44, and VQ44 Packages
Lead-Free (Pb-Free) Packaging
Description
Xilinx introduces the XC18V00 series of in-system
programmable configuration PROMs (Figure 1). Devices in
this 3.3V family include a 4-megabit, a 2-megabit, a
1-megabit, and a 512-kilobit PROM that provide an easy-to-
use, cost-effective method for reprogramming and storing
Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after CE and OE are enabled, data is available on the
PROM DATA (D0) pin that is connected to the FPGA DIN
pin. New data is available a short access time after each
rising clock edge. The FPGA generates the appropriate
number of clock pulses to complete the configuration. When
the FPGA is in Slave Serial mode, the PROM and the FPGA
are clocked by an external clock.
X-Ref Target - Figure 1
CLK CE
When the FPGA is in Master SelectMAP mode, the FPGA
generates a configuration clock that drives the PROM. When
the FPGA is in Slave Parallel or Slave SelectMAP mode, an
external oscillator generates the configuration clock that
drives the PROM and the FPGA. After CE and OE are
enabled, data is available on the PROM’s DATA (D0-D7)
pins. New data is available a short access time after each
rising clock edge. The data is clocked into the FPGA on the
following rising edge of the CCLK. A free-running oscillator
can be used in the Slave Parallel or Slave SelecMAP modes.
Multiple devices can be cascaded by using the CEO output
to drive the CE input of the following device. The clock
inputs and the DATA outputs of all PROMs in this chain are
interconnected. All devices are compatible and can be
cascaded with other members of the family or with the
XC17V00 one-time programmable serial PROM family.
OE/RESET
TCK
Control
Data
Serial
CEO
TMS
TDI
and
JTAG
Address
Memory
Data
or
Parallel
D0 DATA
Serial or Parallel Mode
Interface
Interface
7 D[1:7]
TDO
Parallel Interface
CF
Figure 1: XC18V00 Series Block Diagram
DS026_01_040204
© 1999–2008, 2015 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in
the United States and other countries.
DS026 (v6.0) August 5, 2015
Product Specification
www.xilinx.com
1




XC18V512 pdf, 반도체, 판매, 대치품
— PRODUCT OBSOLETE / UNDER OBSOLESCENCE —
R XC18V00 Series In-System-Programmable Configuration PROMs
Pinout Diagrams
NC
NC
TDI
NC
TMS
GND
TCK
VCCO
D4
CF
NC
7
8
9
10
11
12
13
14
15
16
17
PC44/PCG44
Top View
39 NC
38 NC
37 TDO
36 NC
35 D1
34 GND
33 D3
32 VCCO
31 D5
30 NC
29 NC
*See pin descriptions.
DS026_12_20051007
DATA(D0)
D2
CLK
TDI
TMS
TCK
CF/D4*
OE/RESET
D6
CE
1 20
2 19
3 18
4 SO20/ 17
5 SOG20 16
6 Top 15
7 View 14
8 13
9 12
10 11
VCCINT*
VCCO
VCCINT*
TDO
D1
D3
D5
CEO
D7
GND
*See pin descriptions.
DS026_14_102005
TDI
TMS
TCK
D4/CF*
OE/RESET
4 18
5 PC20/ 17
6 PCG20 16
7 Top View 15
8 14
VCCINT*
TDO
D1
D3
D5
NC
NC
TDI
NC
TMS
GND
TCK
VCCO
D4
CF
NC
1
2
3
4
5
6
7
8
9
10
11
VQ44/VQG44
Top View
33 NC
32 NC
31 TDO
30 NC
29 D1
28 GND
27 D3
26 VCCO
25 D5
24 NC
23 NC
*See pin descriptions.
DS026_15_20051007
*See pin descriptions.
DS026_13_20051007
DS026 (v6.0) August 5, 2015
Product Specification
www.xilinx.com
4

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XC18V512 전자부품, 판매, 대치품
— PRODUCT OBSOLETE / UNDER OBSOLESCENCE —
R XC18V00 Series In-System-Programmable Configuration PROMs
IEEE 1149.1 Boundary-Scan (JTAG)
The XC18V00 family is fully compliant with the IEEE Std.
1149.1 Boundary-Scan, also known as JTAG. A Test
Access Port (TAP) and registers are provided to support all
required Boundary-Scan instructions, as well as many of
the optional instructions specified by IEEE Std. 1149.1. In
addition, the JTAG interface is used to implement in-system
programming (ISP) to facilitate configuration, erasure, and
verification operations on the XC18V00 device.
Table 4 lists the required and optional Boundary-Scan
instructions supported in the XC18V00. Refer to the IEEE Std.
1149.1 specification for a complete description of Boundary-
Scan architecture and the required and optional instructions.
Table 4: Boundary-Scan Instructions
Boundary-Scan Binary
Command
Code [7:0]
Description
Required Instructions:
BYPASS
11111111 Enables BYPASS
SAMPLE/
PRELOAD
00000001 Enables Boundary-Scan
SAMPLE/PRELOAD
operation
EXTEST
00000000 Enables Boundary-Scan
EXTEST operation
Optional Instructions:
CLAMP
11111010 Enables Boundary-Scan
CLAMP operation
HIGHZ
11111100 All outputs in high-Z state
simultaneously
IDCODE
11111110 Enables shifting out
32-bit IDCODE
USERCODE
11111101 Enables shifting out
32-bit USERCODE
XC18V00 Specific Instructions:
CONFIG
11101110 Initiates FPGA configuration
by pulsing CF pin Low once
Instruction Register
The Instruction Register (IR) for the XC18V00 is eight bits
wide and is connected between TDI and TDO during an
instruction scan sequence. In preparation for an instruction
scan sequence, the instruction register is parallel loaded with
a fixed instruction capture pattern. This pattern is shifted out
onto TDO (LSB first), while an instruction is shifted into the
instruction register from TDI. The detailed composition of the
instruction capture pattern is illustrated in Figure 3.
The ISP Status field, IR(4), contains logic “1” if the device is
currently in ISP mode; otherwise, it contains logic “0”. The
Security field, IR(3), contains logic “1” if the device has been
programmed with the security option turned on; otherwise, it
contains logic “0”.
X-Ref Target - Figure 3
IR[7:5] IR[4] IR[3] IR[2] IR[1:0]
TDI
000
ISP
Status
Security
0
01(1) TDO
Notes:
1. IR[1:0] = 01 is specified by IEEE Std. 1149.1
Figure 3: Instruction Register Values Loaded into IR as
Part of an Instruction Scan Sequence
Boundary-Scan Register
The Boundary-Scan register is used to control and observe
the state of the device pins during the EXTEST,
SAMPLE/PRELOAD, and CLAMP instructions. Each output
pin on the XC18V00 has two register stages that contribute
to the Boundary-Scan register, while each input pin only has
one register stage.
For each output pin, the register stage nearest to TDI controls
and observes the output state, and the second stage closest to
TDO controls and observes the high-Z enable state of the pin.
For each input pin, the register stage controls and observes
the input state of the pin.
Identification Registers
The IDCODE is a fixed, vendor-assigned value that is used
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32 bits
wide. The IDCODE register can be shifted out for
examination by using the IDCODE instruction. The IDCODE
is available to any other system component via JTAG.
See Table 5 for the XC18V00 IDCODE values.
The IDCODE register has the following binary format:
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
where
v = the die version number
f = the family code (50h for XC18V00 family)
a = the ISP PROM product ID (26h or 36h for the XC18V04)
c = the company code (49h for Xilinx)
Note: The LSB of the IDCODE register is always read as logic “1”
as defined by IEEE Std. 1149.1.
Table 5 lists the IDCODE register values for XC18V00 devices.
Table 5: IDCODES Assigned to XC18V00 Devices
ISP-PROM
IDCODE
XC18V01
05024093h or <v>5034093h
XC18V02
05025093h or <v>5035093h
XC18V04
05026093h or <v>5036093h
XC18V512
05023093h or <v>5033093h
Notes:
1. The <v> in the IDCODE field represents the device’s revision
code (in hex), and may vary.
DS026 (v6.0) August 5, 2015
Product Specification
www.xilinx.com
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XC18V512

In-System Programmable Configuration PROMs

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