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PDF STK8312 Data sheet ( Hoja de datos )
| Número de pieza | STK8312 | |
| Descripción | Digital Output 3-axis MEMS Accelerometer | |
| Fabricantes | Sensortek | |
| Logotipo |  |
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STK8312
Digital Output 3-axis MEMS Accelerometer
Preliminary Datasheet
Version - 0.9.9
2012/12/13
1 page  
STK8312 REV 0.9.9
4. ELECTRICAL SPECIFICATIONS
TA = 25°C, VS = 2.8 V, VDD I/O = 2.8 V, acceleration = 0 g, CS = CI/O = 10 µF and 0.1 µF
Parameter
POWER SUPPLY
Operating Voltage Range (VS)
Interface Voltage Range (VDD I/O)
Current consumption in active mode
Current consumption in standby mode
Digital high level input voltage (VIH)
Digital low level input voltage (VIL)
High level output voltage (VOH)1
Low level output voltage (VOL)1
OUTPUT DATA RATE AND BANDWIDTH
Output data rate (ODR)
Bandwidth (BW)
1. IOL = 10mA, IOH = -4mA
Test Conditions
Each axis
in active mode
Min
Typ
Max
Unit
2.4 2.8 3.6 V
1.7 3.6 V
184 µA
1 µA
0.7 x VDD I/O
V
0.3 x VDD I/O V
0.8 x VDD I/O
V
0.2 x VDD I/O V
3.125
400 Hz
ODR/2
Hz
www.sensortek.com.tw
4 @copyright 2013 Sensortek Technology Corp.
5 Page 
STK8312 REV 0.9.9
9. REGISTER DEFINATION
Address Name
Definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
$00
XOUT
6/8-bit output value X Rev/XOUT[7] Alert/XOUT[6] XOUT[5]
XOUT[4] XOUT[3] XOUT[2] XOUT[1]
$01
YOUT
6/8-bit output value Y Rev/YOUT[7] Alert/YOUT[6] YOUT[5]
YOUT[4] YOUT[3] YOUT[2] YOUT[1]
$02
ZOUT
6/8-bit output value Z
Rev/ZOUT[7] Alert/ZOUT[6]
ZOUT[5]
ZOUT[4] ZOUT[3] ZOUT[2] ZOUT[1]
$03 TILT
Tilt Status
Shake
Alert
Tap
PoLa[2]
PoLa[1]
PoLa[0] BaFro[1]
$04
SRST
Sampling Rate Status
0
0
0
0
FFAL
DTap
Reserved
$05 Reserved
Reserved
Reserved
Reserved
Reserved Reserved Reserved Reserved Reserved
$06 INTSU
Interrupt Setup
SHINTX
SHINTY
SHINTZ
GINT
Reserved PDINT
PLINT
$07 MODE
Mode
IAH
IPP
Reserved Reserved Reserved
TON
Reserved
$08 SR
Portrait/Landscape
samples
per seconds and
Debounce
Filter
FILT[2]
FILT[1]
FILT[0]
Reserved Reserved AMSR[2] AMSR[1]
$09 PDET
Tap Detection
ZDA
YDA
XDA
PDTH[4] PDTH[3] PDTH[2] PDTH[1]
$0A
Reserved
Reserved
Reserved
Reserved
Reserved Reserved Reserved Reserved Reserved
$0B
Reserved
Reserved
Reserved
Reserved
Reserved Reserved Reserved Reserved Reserved
$0C OFSX
X-Axis offset
OFSX[7]
OFSX[6]
OFSX[5]
OFSX[4] OFSX[3] OFSX[2] OFSX[1]
$0D OFSY
Y-Axis offset
OFSY[7]
OFSY[6]
OFSY[5]
OFSY[4] OFSY[3] OFSY[2] OFSY[1]
$0E OFSZ
Z-Axis offset
OFSZ[7]
OFSZ[6]
OFSZ[5]
OFSZ[4] OFSZ[3] OFSZ[2] OFSZ[1]
$0F PLAT
Tap Latency
PLAT[7]
PLAT[6]
PLAT[5]
PLAT[4] PLAT[3] PLAT[2] PLAT[1]
$10 PWIN
Tap Window
PWIN[7]
PWIN[6]
PWIN[5]
PWIN[4] PWIN[3] PWIN[2] PWIN[1]
$11 FTH Free-Fall Threshold
FTH[7]
FTH[6]
FTH[5]
FTH[4]
FTH[3]
FTH[2]
FTH[1]
$12 FTM
Free-Fall Time
FTM[7]
FTM[6]
FTM[5]
FTM[4]
FTM[3]
FTM[2]
FTM[1]
$13 STH
Shake Threshold
RNG[1]
RNG[0]
-
-
-
STH[2]
STH[1]
$14 CTRL
Control Register
-
-
AOI - FFINT
$20 SWRST
Software Reset
SWRST[7]
SWRST[6]
SWRST[5]
SWRST[4] SWRST[3] SWRST[2] SWRST[1]
NOTE: To write to the registers the MODE bit in the MODE (0x07) register must be set to 0, placing the device in Standby Mode.
Bit 0
XOUT[0]
YOUT[0]
ZOUT[0]
BaFro[0]
AMSRS
Reserved
FBINT
MODE
AMSR[0]
PDTH[0]
Reserved
Reserved
OFSX[0]
OFSY[0]
OFSZ[0]
PLAT[0]
PWIN[0]
FTH[0]
FTM[0]
STH[0]
DPINT
SWRST[0]
$00: 6/8-bits output value X (Read Only)
XOUT — X Output
D7 D6 D5 D4 D3 D2 D1 D0
Rev/XOUT[7] Alert/XOUT[6] XOUT[5]
XOUT[4]
XOUT[3]
XOUT[2]
XOUT[1] XOUT[0]
0 0 0 0 0 0 00
If the RNG[1:0] of STH register is clear, then D0~D5 is signed byte 6-bit 2’s complement data with allowable range of
+31 to -32. XOUT[5] is 0 if the g direction is positive, 1 if the g direction is negative. D6 is used as alert bit. If the Alert
bit is set, the register was read at the same time as the device was attempting to update the contents. The register
must be read again. D7 is a reserved bit.
If the RNG[1:0] of STH register is set, then D0~D7 is signed byte 8-bit 2’s complement data with allowable range of
+127 to -128. XOUT[7] is 0 if the g direction is positive. 1 if the g direction is negative.
$01: 6/8-bits output value Y (Read Only)
YOUT — Y Output
D7 D6 D5 D4 D3 D2 D1 D0
Rev/YOUT[7] Alert/YOUT[6] YOUT[5]
YOUT[4]
YOUT[3]
YOUT[2]
YOUT[1] YOUT[0]
0 0 0 0 0 0 00
If the RNG[1:0] of STH register is clear, then D0~D5 is signed byte 6-bit 2’s complement data with allowable range of
+31 to -32. YOUT[5] is 0 if the g direction is positive, 1 if the g direction is negative. D6 is used as alert bit. If the Alert
bit is set, the register was read at the same time as the device was attempting to update the contents. The register
must be read again. D7 is a reserved bit.
If the RNG[1:0] of STH register is set, then D0~D7 is signed byte 8-bit 2’s complement data with allowable range of
+127 to -128. YOUT[7] is 0 if the g direction is positive. 1 if the g direction is negative.
www.sensortek.com.tw
10 @copyright 2013 Sensortek Technology Corp.
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet STK8312.PDF ] | |
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