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ST-PLC-AFE 데이터시트 PDF




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부품번호 ST-PLC-AFE 기능
기능 analog front-end
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ST-PLC-AFE 데이터시트, 핀배열, 회로
ST-PLC-AFE
Power-line communication, analog front-end
Features
Integrated, analog power-line driver and
receiver
EN 50065-1 - CENELEC, European bands A,
B, C, and D
Supports FSK, S-FSK, and OFDM
Supports PRIME, G3, and IEC 61334
Half-duplex mode
Thermal protection
Programmable overcurrent protection
10 V p-p single-ended output range
20 V p-p differential-ended output range
Programmable transmitter chain (Tx) and
receiver chain (Rx) filters
Programmable Rx and Tx gain control
7 V to 14 V line driver supply
Low power consumption: 10 mW (receive
mode)
Reverse sensitivity 20 µVrms typical
Four-wire, serial peripheral interface
Two integrated zero cross detectors
Temperature range: -40 °C to 125 °C
Datasheet - production data
Applications
E-metering
Smart grid applications
Smart light control
Solar energy management
Building automation
Remote monitoring and control
Description
The ST-PLC-AFE is a power-line communication,
analog front-end device capable of capacitive or
transformer-coupled connections to the power
line while under the control of a microcontroller or
a DSP.
The line driver is able to drive low-impedance
lines, requiring up to 1.65 A, into reactive loads. It
can also work in differential mode for high
performance, as well as single-ended mode for a
low-cost bill of materials (BOM). The integrated
receiver is able to detect signals down to 20
µVrms. The system works in half-duplex mode.
The AFE is protected against over temperature
and short-circuit conditions. It also provides four
adjustable current limits through an internal
register. Through the four-wire serial peripheral
interface, or SPI, each functional block can be
enabled or disabled to optimize power
consumption.
February 2016
This is information on a product in full production.
DocID028727 Rev 1
1/58
www.st.com




ST-PLC-AFE pdf, 반도체, 판매, 대치품
Package pin description and connections
1 Package pin description and connections
ST-PLC-AFE
Pin no.
Name
1 ZC1_OUT
2 ZC1_IN
3 DVDD
4 DGND
5 NC1
6 nCS
7 EN
8 SCLK
9 DIN
10 DOUT
11 DAC_CLK
12 NC2
13 INT
14 TX_INP
15 TX_INN
16 AGND
17 AVDD
18 TX_OUTN
19 TX_OUTP
20 NC3
21 NC4
22 MID_AVDD
23 THERMAL
24 MID_PA_VDD
25 PA_INP
26 PA_INN
27 PA_VDD
28 PA_VDD
29 PA_OUTN
30 PA_OUTN
Table 1. QFN48 pin description
Type
Description
OUT ANALOG
Zero cross detector 1 output node
IN ANALOG
POWER DIGITAL
NC
Zero cross detector 1 input node
Digital positive supply
Digital ground
Not connected to the Silicon
IN DIGITAL
SPI digital select
System enable
SPI serial clock
SPI digital input
OUT
SPI digital output
IN DIGITAL
DAC input frequency
NC Not connected to the Silicon
OUT DIGITAL
Interrupt on overcurrent or thermal limit
IN ANALOG
DAC output (positive side)
DAC output (negative side)
Analog ground
POWER ANALOG
Analog positive supply
OUT ANALOG
Tx LPF output (negative side)
Tx LPF output (positive side)
NC Not connected to the Silicon
OUT ANALOG
IN ANALOG
Rx common mode voltage, AVDD/2 to be
connected to 150 nF capacitor
Thermal sensor output voltage, to be connected
to an ADC
PA common mode voltage, PA supply voltage
divided by 2, to be connected to 10 nF capacitor
PA non inverting input
PA inverting input
POWER PA
Power amplifier positive supply
OUT PA
PA output inverting side
4/58 DocID028727 Rev 1

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ST-PLC-AFE 전자부품, 판매, 대치품
ST-PLC-AFE
2 General description
General description
The ST-PLC-AFE combines a digital-to-analog converter (DAC), an adaptive gain control
(AGC), programmable filters, and a line driver on a single chip. The architecture is divided
into three primary functional blocks:
Power amplifier (PA)
The PA is characterized by the following features:
– Differential or single-ended output architecture
– 1.65 A drive capability @ 14 Vpp
– Gain of 6.9 V/V
– PA current limiter with four programmable limits: 0.5 A, 1 A, 1.5 A, and 2.1 A
– Integrated thermometer placed closed to the PA
Transmitter chain (Tx)
The Tx is characterized by the following features:
– Can work with a 10-bit internal DAC
– Can be driven with an external DAC through the TX_INP input pin
– Programmable unity-gain fourth-order low-pass filter, following CENELEC bands
A, B, C, and D.
– PGA with gains of 6 dB, 0 dB, -18 dB, and -36 dB
Receiver chain (Rx)
The Rx is characterized by the following features:
– PGA1 with gains of -3 dB, 3 dB, 9 dB, and 15 dB
– Sensitivity of 20 µVrms typical
– Can be connected in differential or single-input mode
– Programmable unity-gain fourth-order low-pass filter, following CENELEC bands
A, B, C, and D.
– Selectable high-pass filter with a 35 kHz cutoff frequency)
– PGA2 with gains of -6 dB, 6 dB, 18 dB, and 30 dB
The ST-PLC-AFE supports other circuitry blocks, such as:
SPI interface for the microcontroller
Thermal shutdown
Two zero crossing detectors
DocID028727 Rev 1
7/58
58

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ST-PLC-AFE

analog front-end

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