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PDF P3C1256L Data sheet ( Hoja de datos )
| Número de pieza | P3C1256L | |
| Descripción | STATIC CMOS RAM | |
| Fabricantes | PYRAMID | |
| Logotipo |  |
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FEATURES
VCC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70/85
Wide Range Power Supply: 2.7V to 3.6V
Easy Memory Expansion Using CE and OE Inputs
Common Data I/O
P3C1256L
LOW POWER 32K x 8
STATIC CMOS RAM
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
— 28-Pin 600 mil DIP
— 28-Pin 330 mil SOP
— 28-Pin TSOP
DESCRIPTION
The P3C1256L is a 262,144-bit low power CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access and
cycle times. Inputs are fully TTL-compatible. The RAM
operates with a wide range power supply (2.7V to 3.6V).
Access times of 55 ns and 70 ns are available. CMOS is
utilized to reduce power consumption to a low level.
The P3C1256L device provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pins A0 to A14. Reading is accom-
plished by device selection (CE and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE or OE is HIGH or WE is LOW.
Functional Block Diagram
Pin ConfigurationS
Document # SRAM143 REV A
DIP (P6), SOP (S11-3)
TOP VIEW
Revised October 2011
1 page  
AC CHARACTERISTICS—WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol Parameter
-55
Min Max
tWC Write Cycle Time
55
tCW Chip Enable Time to End of Write
50
tAW Address Valid to End of Write
tAS Address Setup Time
50
0
tWP Write Pulse Width
tAH Address Hold Time
40
0
tDW Data Valid to End of Write
25
tDH Data Hold Time
tWZ Write Enable to Output in High Z
0
25
tOW Output Active from End of Write
5
P3C1256L - 32K x 8 STATIC CMOS RAM
-70
Min Max
70
60
60
0
50
0
30
0
30
5
-85
Min Max
85
75
75
0
60
0
35
0
35
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(10,11)
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM143 REV A
Page 5
5 Page 
P3C1256L - 32K x 8 STATIC CMOS RAM
REVISIONS
DOCUMENT NUMBER SRAM143
DOCUMENT TITLE
P3C1256L LOW POWER 32K x 8 STATIC CMOS RAM
REV
OR
A
ISSUE DATE
Jul-2011
Oct-2011
ORIGINATOR DESCRIPTION OF CHANGE
JDB New Data Sheet
JDB Added wide range power supply
Document # SRAM143 REV A
Page 11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet P3C1256L.PDF ] | |
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