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P4C1041L 데이터시트 PDF




PYRAMID에서 제조한 전자 부품 P4C1041L은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 P4C1041L 기능
기능 STATIC CMOS RAM
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P4C1041L 데이터시트, 핀배열, 회로
FEATURES
Fast Access Time - 55 ns
Low Power Operation
Single 5V±10% Power Supply
2.0V Data Retention
Easy Memory Expansion Using CE and OE Inputs
Fully TTL Compatible Inputs and Outputs
P4C1041L
LOW POWER 256K x 16 (4 MEG)
STATIC CMOS RAM
Advanced CMOS Technology
Fast tOE
Automatic Power Down when deselected
Packages
– 44-Pin 400 mil TSOP II
DESCRIPTION
The P4C1041L is a 262,144 words by 16 bits high-speed
CMOS static RAM. The CMOS memory requires no clocks
or refreshing, and has equal access and cycle times. In-
puts are fully TTL-compatible. The RAM operates from a
single 5.0V ± 10% tolerance power supply.
Access times of 55 nanoseconds permit greatly enhanced
system operating speeds. CMOS is utilized to reduce
power consumption to a low level.
The P4C1041L device provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pins A0 to A17. Reading is accom-
plished by device selection (CE) and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE or OE is HIGH or WE is LOW.
The P4C1041L comes in a 44-Pin 400 mil TSOP II pack-
age.
Functional Block Diagram
Pin Configuration
Document # SRAM142 REV OR
TSOP II
Revised March 2011




P4C1041L pdf, 반도체, 판매, 대치품
TIMING WAVEFORM OF READ CYCLE NO. 1
P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM
TIMING WAVEFORM OF READ CYCLE NO. 2 (OE CONTROLLED)(5,6)
Notes:
1. Stresses greater than those listed under Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to Maximum rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –2.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM142 REV OR
Page 4

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P4C1041L 전자부품, 판매, 대치품
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM
Figure 1. Output Load
* including scope and test fixture.
Figure 2. Thevenin Equivalent
Note:
Because of the ultra-high speed of the P4C1041L, care must be taken
when testing this device; an inadequate setup can cause a normal function-
ing part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at
the comparator input, and a 589Ω resistor must be used in series with
DOUT to match 639Ω (Thevenin Resistance).
TRUTH TABLE
Mode
Powerdown
Read All Bits
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
CE OE WE BLE BHE I/O0 - I/O7 I/O8 - I/O15
HXXXX
High Z
High Z
L LHL L
L LHLH
L LHH L
LXL L L
LXL LH
LXLHL
LHHXX
DOUT
DOUT
High Z
DIN
DIN
High Z
High Z
DOUT
High Z
DOUT
DIN
High Z
DIN
High Z
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Document # SRAM142 REV OR
Page 7

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부품번호상세설명 및 기능제조사
P4C1041L

STATIC CMOS RAM

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