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P4C1299L 데이터시트 PDF




PYRAMID에서 제조한 전자 부품 P4C1299L은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 P4C1299L 기능
기능 STATIC CMOS RAM
제조업체 PYRAMID
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P4C1299L 데이터시트, 핀배열, 회로
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 15/20/25/35 ns (Commercial/Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation
Single 5V±10% Power Supply
Output Enable (OE) & Chip Enable (CE1 and CE2)
Control Functions
P4C1299/P4C1299L
ULTRA HIGH SPEED 64K x 4
STATIC CMOS RAM
Data Retention with 2.0V Supply (P4C1299L)
Three-State Outputs
TTL/CMOS Compatible Outputs
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350x550 mil LCC
DESCRIPTION
The P4C1299 and P4C1299L are a 262,144-bit ultra high-
speed static RAM organized as 64K x 4.The CMOS memory
requires no clock or refreshing and has equal access and
cycle times. Inputs and outputs are fully TTL-compatible.
The RAM operates from a single 5V±10% tolerance power
supply. With battery backup (P4C1299LOnly), data integrity
is maintained for supply voltages down to 2.0V. Current
drain is typically 10 µA from a 2.0V supply.
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption.
The P4C1299 and P4C1299L are available in a 28-pin
300 mil DIP or SOJ, as well as a 28-pin 350x550 mil LCC
package, providing excellent board level densities.
Functional Block Diagram
Pin ConfigurationS
Document # SRAM144 REV OR
DIP (P5, C5)
SOJ (J5)
LCC (L5)
Created Nov 2012




P4C1299L pdf, 반도체, 판매, 대치품
P4C1299/P4C1299L - ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE1,2 CONTROLLED)(5,6)
Notes:
1. Stresses greater than those listed under Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to Maximum rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
5. CE1 and CE2 are LOW and WE is HIGH for READ cycle.
6. WE is HIGH and ADDRESS must be valid prior to, or coincident with
CE1 and CE2 transitions LOW.
7. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM144 REV OR
Page 4

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P4C1299L 전자부품, 판매, 대치품
P4C1299/P4C1299L - ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM
Figure 1. Output Load
* including scope and test fixture.
Figure 2. Thevenin Equivalent
Note:
Because of the ultra-high speed of the P4C1299, care must be taken when
testing this device; an inadequate setup can cause a normal function-
ing part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOUT to match 166Ω (Thevenin Resistance).
Document # SRAM144 REV OR
Page 7

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관련 데이터시트

부품번호상세설명 및 기능제조사
P4C1299

STATIC CMOS RAM

PYRAMID
PYRAMID
P4C1299L

STATIC CMOS RAM

PYRAMID
PYRAMID

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