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P4C164LL 데이터시트 PDF




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부품번호 P4C164LL 기능
기능 STATIC CMOS RAM
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P4C164LL 데이터시트, 핀배열, 회로
FEATURES
VCC Current (Commercial/Industrial)
— Operating: 55 mA
— CMOS Standby: 3 µA
Access Times
—80/100 (Commercial or Industrial)
—90/120 (Military)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE1, CE2 and OE
Inputs
P4C164LL
VERY LOW POWER 8Kx8
STATIC CMOS RAM
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin 300 and 600 mil DIP
—28-Pin 330 mil SOP
DESCRIPTION
The P4C164LL is a 64K density low power CMOS static
RAM organized as 8Kx8. The CMOS memory requires
no clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply.
Access times of 80 and 100 ns are available for commercial
and industrial temperatures; access times of 90 and 100
ns are available for military temperature. CMOS is utilized
to reduce power consumption to a low level.
The P4C164LL device provides asynchronous operation
with matching access and cycle times.
Memory locations are specified on address pins A0 to A12.
Reading is accomplished by device selection (CE1 LOW,
CE2 HIGH ) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory loca-
tion is presented on the data input/output pins. The input/
output pins stay in the HIGH Z state when either CE1 or
OE is HIGH or WE or CE2 is LOW.
Package options for the P4C164LL include 28-pin 300 and
600 mil DIP and 28-pin 330 mil SOP packages.
Functional Block Diagram
Pin ConfigurationS
Document # SRAM116 REV 04
DIP (P5, P6, C5-1), SOP (S5)
TOP VIEW
Revised June 2014




P4C164LL pdf, 반도체, 판매, 대치품
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(1)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)
Notes:
5. WE is HIGH for READ cycle.
6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE1 transition LOW
and CE2 transition HIGH.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
Document # SRAM116 REV 04
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays ir-
respective of whether CE1 or CE2 causes them.
Page 4

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P4C164LL 전자부품, 판매, 대치품
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Condition
Min Typ. * VCC =
Max VCC =
Unit
2.0V 3.0V 2.0V 3.0V
VDR VCC for Data Retention
2.0 V
ICCDR Data Retention Current
CE1 ≥ VCC - 0.2V or
1 2 3 4 µA
tCDR Chip Deselect to Data Retention Time CE2 ≤ 0.2V, VIN ≥ VCC - 0.2V or 0
ns
tR† Operation Recovery Time
VIN ≤ 0.2V
tRC§
ns
* TA = +25°C
§tRC = Read Cycle Time
† This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
ORDERING INFORMATION
Document # SRAM116 REV 04
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부품번호상세설명 및 기능제조사
P4C164LL

STATIC CMOS RAM

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