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P4C1982L 데이터시트 PDF




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부품번호 P4C1982L 기능
기능 STATIC CMOS RAM
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P4C1982L 데이터시트, 핀배열, 회로
P4C1981/P4C1981L, P4C1982/P4C1982L
ULTRA HIGH SPEED 16K x 4
CMOS STATIC RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation (Commercial/Military)
Output Enable and Dual Chip Enable Functions
5V ± 10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical
Current (P4C1981L/1982L Military)
Separate Inputs and Outputs
– P4C1981/L Input Data at Outputs during Write
– P4C1982/L Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
– 28-Pin CERPACK
DESCRIPTION
The P4C1981/L and P4C1982/L are 65,536-bit (16Kx4)
ultra high-speed static RAMs similar to the P4C198, but
with separate data I/O pins. The P4C1981/L feature a
transparent write operation when OE is low; the outputs
of the P4C1982/L are in high impedance during the write
cycle. All devices have low power standby modes. The
RAMs operate from a single 5V ± 10% tolerance power
supply. With battery backup, data integrity is maintained
for supply voltages down to 2.0V. Current drain is
typically 10 µA from 2.0V supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption. For the
P4C1982L and P4C1981L, power is only 5.5 mW standby
with CMOS input levels.
The P4C1981/L and P4C1982/L are available in 28-pin 300
mil DIP and SOJ, 28-pin 350x550 mil LCC and a 28-pin
CERPACK package providing excellent board level den-
sities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P5, C5, D5-2), SOJ (J5)
CERPACK (F4) SIMILAR
P4C1981/ 1982
LCC (L5)
Document # SRAM114 REV B
Revised August 2006
1




P4C1982L pdf, 반도체, 판매, 대치품
P4C1981/1981L, P4C1982/1982L
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym. Parameter
-10 -12
Min Max Min Max
tRC Read Cycle Time 10
12
tAA Address Access 10 12
Time
tAC Chip Enable
Access Time
10 12
tOH Output Hold from 2
Address Change
2
tLZ Chip Enable to
Output in Low Z
2
2
tHZ Chip Disable to
67
Output in High Z
tOE Output Enable
Low to Data Valid
6
7
tOLZ Output Enable to
Output in Low Z
2
2
tOHZ Output Disable to
Output in High Z
6
7
tPU Chip Enable to
Power Up Time
0
0
tPD Chip Disable to
Power Down Time
10
12
-15
Min Max
15
15
15
2
2
8
8
2
9
0
15
-20 -25
Min Max Min Max
20 25
20 25
20 25
22
22
10 10
12 15
22
9 10
00
20 25
-35
Min Max
35
35
35
2
2
15
21
2
14
0
25
-45 Unit
Min Max
45 ns
45 ns
45 ns
2 ns
2 ns
15 ns
27 ns
2 ns
15 ns
0 ns
30 ns
READ CYCLE NO.1 (OE controlled)(5)
Notes:
5. WE is HIGH for READ cycle.
6. CE1, CE2 and OE are LOW for READ Cycle.
7. OE is LOW for the cycle.
8. ADDRESS must be valid prior to or coincident with, CE1, and
CE2 transition LOW.
Document # SRAM114 REV B
9. Transition is measured ±200mV from steady state voltage
prior to change, with loading as specified in Figure 1.
10. Read Cycle Time is measured from the last valid address to
the first transitioning address.
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P4C1982L 전자부품, 판매, 대치품
WRITE CYCLE NO. 2 (WE CONTROLLED)(13,14)
P4C1981/1981L, P4C1982/1982L
WRITE CYCLE NO. 3 (CE1, CE2 CONTROLLED)(11,12)
1520 08
Notes:
12. CE (CE1, CE2) and WE must be LOW for WRITE cycle.
13. OE is LOW for WRITE cycle.
14. If CE1 or CE2 goes HIGH simultaneously with WE HIGH, the
output remains in a high impedance state.
15. Write Cycle Time is measured from the last valid address to the
first transitioning address.
Document # SRAM114 REV B
Page 7 of 13

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부품번호상세설명 및 기능제조사
P4C1982

STATIC CMOS RAM

PYRAMID
PYRAMID
P4C1982L

STATIC CMOS RAM

PYRAMID
PYRAMID

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