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부품번호 | STP110N8F7 기능 |
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기능 | N-channel Power MOSFET | ||
제조업체 | STMicroelectronics | ||
로고 | |||
전체 13 페이지수
STP110N8F7
N-channel 80 V, 6.4 mΩ typ., 80 A, STripFET™ F7
Power MOSFET in a TO-220 package
Datasheet - production data
Figure 1: Internal schematic diagram
Features
Order code
STP110N8F7
VDS
80 V
RDS(on)max
7.5 mΩ
ID
80 A
PTOT
170 W
Among the lowest RDS(on) on the market
Excellent figure of merit (FoM)
Low Crss/Ciss ratio for EMI immunity
High avalanche ruggedness
Applications
Switching applications
Description
This N-channel Power MOSFET utilizes
STripFET™ F7 technology with an enhanced
trench gate structure that results in very low on-
state resistance, while also reducing internal
capacitance and gate charge for faster and more
efficient switching.
Order code
STP110N8F7
Table 1: Device summary
Marking
Package
110N8F7
TO-220
Packaging
Tube
November 2015
DocID027154 Rev 2
This is information on a product in full production.
1/13
www.st.com
Electrical characteristics
STP110N8F7
2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4: On /off states
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source
breakdown voltage
VGS = 0, ID = 250 µA
Zero gate voltage
IDSS drain current
VGS = 0, VDS = 80 V
VGS = 0, VDS = 80 V,
TC = 125 °C
Gate-body leakage
IGSS current
VDS = 0, VGS = ± 20 V
VGS(th)
Gate threshold
voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source
on- resistance
VGS = 10 V, ID = 40 A
Min.
80
Typ. Max. Unit
V
1 µA
10 µA
±100 nA
2.5 4.5 V
6.4 7.5 mΩ
Symbol
Ciss
Coss
Crss
Qg
Qgs
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Total gate charge
Gate-source charge
Qgd Gate-drain charge
Table 5: Dynamic
Test conditions
VGS = 0, VDS = 40 V,
f = 1 MHz
VDD = 40 V, ID = 80 A,
VGS = 10 V
(see Figure 14: "Test
circuit for gate charge
behavior" )
Min.
-
-
-
-
-
-
Typ.
3435
653
57
46.8
23.4
11.2
Max.
-
-
Unit
pF
pF
- pF
- nC
- nC
- nC
Symbol
td(on)
tr
td(off)
Parameter
Turn-on delay time
Rise time
Turn-off delay time
tf Fall time
Table 6: Switching times
Test conditions
VDD = 40 V, ID = 40 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 13: "Test
circuit for resistive load
switching times" and
Figure 18: "Switching time
waveform" )
Min.
-
-
-
-
Typ.
49
95
60
32
Max.
-
-
-
Unit
ns
ns
ns
- ns
4/13 DocID027154 Rev 2
4페이지 STP110N8F7
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs
temperature
Figure 10: Normalized on-resistance vs
temperature
Figure 11: Normalized V(BR)DSS vs temperature
Figure 12: Source-drain diode forward characteristics
DocID027154 Rev 2
7/13
7페이지 | |||
구 성 | 총 13 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
STP110N8F7 | N-channel Power MOSFET | STMicroelectronics |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |