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부품번호 | STP12N50M2 기능 |
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기능 | N-channel Power MOSFET | ||
제조업체 | STMicroelectronics | ||
로고 | |||
전체 13 페이지수
STP12N50M2
N-channel 500 V, 0.325 Ω typ.,10 A MDmesh II Plus™ low Qg
Power MOSFET in a TO-220 package
Datasheet - preliminary data
7$%
72
Features
Order code
STP12N50M2
VDS
500 V
RDS(on) max ID
0.38 Ω 10 A
• Extremely low gate charge
• Lower RDS(on) x area vs previous generation
• Low gate input resistance
• 100% avalanche tested
• Zener-protected
Figure 1. Internal schematic diagram
, TAB
Applications
• Switching applications
Description
This device is an N-channel Power MOSFET
developed using a new generation of MDmesh™
technology: MDmesh II Plus™ low Qg. This
revolutionary Power MOSFET associates a
vertical structure to the company's strip layout to
yield one of the world's lowest on-resistance and
gate charge. It is therefore suitable for the most
demanding high efficiency converters.
AM15572v1
Order code
STP12N50M2
.
Table 1. Device summary
Marking
Package
12N50M2
TO-220
Packaging
Tube
June 2014
DocID026516 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/13
www.st.com
Electrical characteristics
2 Electrical characteristics
STP12N50M2
(TC = 25 °C unless otherwise specified)
Symbol
Parameter
Table 5. On /off states
Test conditions
Drain-source
V(BR)DSS breakdown voltage
ID = 1 mA, VGS = 0
Zero gate voltage
IDSS
drain current
IGSS
Gate-body leakage
current
VGS = 0, VDS = 500 V
VGS = 0, VDS = 500 V,
TC=125 °C
VDS = 0, VGS = ± 25 V
VGS(th)
RDS(on)
Gate threshold voltage VDS = VGS, ID = 250 μA
Static drain-source
on-resistance
VGS = 10 V, ID = 5 A
Min. Typ. Max. Unit
500 V
1 μA
100 μA
±10 μA
2 3 4V
0.325 0.38 Ω
Symbol
Parameter
Table 6. Dynamic
Test conditions
Min. Typ. Max. Unit
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VGS = 0, VDS = 100 V,
f = 1 MHz
- 560 - pF
- 33 - pF
- 1 - pF
(1) Equivalent output
Coss eq. capacitance
VGS = 0, VDS = 0 to 400 V
- 125 - pF
Intrinsic gate
RG resistance
f = 1 MHz open drain
- 6.8 - Ω
Qg Total gate charge
VDD = 400 V, ID = 10 A,
Qgs Gate-source charge VGS = 10 V (see Figure 15)
Qgd Gate-drain charge
- 15 - nC
- 3 - nC
- 8.3 - nC
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
4/13 DocID026516 Rev 1
4페이지 STP12N50M2
Electrical characteristics
Figure 8. Capacitance variations
&
S)
*,3*6$
Figure 9. Output capacitance stored energy
(RVV
-
*,3*6$
&LVV
&RVV
&UVV
9'69
Figure 10. Normalized gate threshold voltage vs
temperature
9*6WK
QRUP
*,3*6$
,' $
7-&
Figure 12. Normalized V(BR)DSS vs temperature
9%5'66
QRUP
*,3*6$
,' P$
7-&
9'69
Figure 11. Normalized on-resistance vs
temperature
5'6RQ
QRUP
9*6 9
*,3*6$
7-&
Figure 13. Source-drain diode forward
characteristics
96'9
*,3*6$
7- &
7- &
7- &
,6'$
DocID026516 Rev 1
7/13
13
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부품번호 | 상세설명 및 기능 | 제조사 |
STP12N50M2 | N-channel Power MOSFET | STMicroelectronics |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |