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부품번호 | STU9HN65M2 기능 |
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기능 | N-channel Power MOSFET | ||
제조업체 | STMicroelectronics | ||
로고 | |||
전체 12 페이지수
STU9HN65M2
N-channel 600 V, 0.71 Ω typ., 5.5 A MDmesh™ M2
Power MOSFET in an IPAK package
Datasheet - production data
TAB
IPAK
3
2
1
Figure 1: Internal schematic diagram
D(2, TAB)
G(1)
Features
Order code
STU9HN65M2
VDS
600 V
RDS(on) max.
0.82 Ω
ID
5.5 A
• Extremely low gate charge
• Excellent output capacitance (COSS) profile
• 100% avalanche tested
• Zener-protected
Applications
• Switching applications
Description
This device is an N-channel Power MOSFET
developed using MDmesh™ M2 technology.
Thanks to its strip layout and an improved vertical
structure, the device exhibits low on-resistance
and optimized switching characteristics,
rendering it suitable for the most demanding high
efficiency converters.
S(3)
AM15572v1_tab
Order code
STU9HN65M2
Table 1: Device summary
Marking
Package
9HN65M2
IPAK
Packing
Tube
April 2015
DocID027605 Rev 2
This is information on a product in full production.
1/12
www.st.com
Electrical characteristics
STU9HN65M2
2 Electrical characteristics
(TC = 25 °C unless otherwise specified).
Table 5: Static
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source
breakdown voltage
VGS = 0 V, ID = 1 mA
VGS = 0 V, VDS = 650 V
IDSS
Zero gate voltage drain
current
VGS = 0 V, VDS = 650 V,
TC = 125 °C
IGSS
Gate-body leakage
current
VDS = 0 V, VGS = ±25 V
VGS(th)
RDS(on)
Gate threshold voltage
Static drain-source on-
resistance
VDS = VGS, ID = 250 µA
VGS = 10 V, ID = 2.5 A
Min. Typ. Max. Unit
650 V
1 µA
100 µA
±10 µA
23 4V
0.71 0.82 Ω
Symbol
Ciss
Coss
Crss
Coss
(1)
eq.
RG
Qg
Qgs
Qgd
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent output
capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
Table 6: Dynamic
Test conditions
VDS= 100 V, f = 1 MHz,
VGS = 0 V
VDS = 0 V to 520 V, VGS = 0 V
f = 1 MHz open drain
VDD = 520 V, ID = 5 A,
VGS = 10 V (see Figure 15:
"Gate charge test circuit")
Min. Typ. Max. Unit
- 325 - pF
- 16 - pF
- 0.85 - pF
- 109 -
- 5.6 -
- 11.5 -
- 2.5 -
-5 -
pF
Ω
nC
nC
nC
Notes:
(1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS.
Symbol
td(on)
tr
td(off)
tf
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Table 7: Switching times
Test conditions
VDD = 325 V, ID = 2.5 A
RG = 4.7 Ω, VGS = 10 V (see
Figure 14: "Switching times
test circuit for resistive load"
and Figure 19: "Switching time
waveform")
Min.
-
-
-
Typ.
7.5
4.6
24
Max.
-
-
-
Unit
ns
ns
ns
- 14.5 -
ns
4/12 DocID027605 Rev 2
4페이지 STU9HN65M2
Figure 8: Static drain-source on-resistance
Electrical characteristics
Figure 9: Normalized on-resistance vs.
temperature
RDS(on)
GIPD180920141459FSR
(norm)
2.2
VGS= 10V
1.8
1.4
1
0.6
0.2
-75 -25 25 75 125 Tj(°C)
Figure 10: Gate charge vs. gate-source
voltage
Figure 11: Capacitance variations
Figure 12: Output capacitance stored energy
Figure 13: Source- drain diode forward
characteristics
DocID027605 Rev 2
7/12
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
STU9HN65M2 | N-channel Power MOSFET | STMicroelectronics |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |