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PDF RJF0613JSP Data sheet ( Hoja de datos )
| Número de pieza | RJF0613JSP | |
| Descripción | Silicon N Channel MOS FET | |
| Fabricantes | Renesas | |
| Logotipo |  |
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Target Specifications Datasheet
RJF0613JSP
60 V - 10 A - N Channel MOS FET
Power Switching
R07DS0874EJ0100
Rev.1.00
Aug 29, 2012
Description
This FET has the over temperature shut-down capability sensing to the junction temperature. This FET has the built-in
over temperature shut-down circuit in the gate area. And this circuit operation to shut-down the gate voltage in case of
high junction temperature like applying over power consumption, over current etc..
Features
Logic level operation (4 V Gate drive).
Built-in the over temperature shut-down circuit.
High endurance capability against to the short circuit.
Latch type shut down operation (need 0 voltage recovery).
Built-in the current limitation circuit.
High density mounting
Power supply voltage applies 12 V and 24 V.
AEC-Q101 Compliant
Outline
RENESAS Package code: PRSP0008DD-D
(Package name: SOP-8 <FP-8DAV> )
8765
1234
G
Gate resistor
Temperature
Sensing
Circuit
Latch
Circuit
Gate
Shut-down
Circuit
Current
Limitation
Circuit
DDDD
1, 2, 3 Source
4 Gate
5, 6, 7, 8 Drain
SSS
Absolute Maximum Ratings
Item
Symbol
Ratings
Drain to source voltage
VDSS
60
Gate to source voltage
Gate to source voltage
Drain current
VGSS
VGSS
ID Note3
16
–2.5
10
Body-drain diode reverse drain current
Avalanche current
Avalanche energy
Channel dissipation
IDR
IAP Note 2
EAR Note 2
Pch Note 1
10
4.7
94.7
2.5
Channel temperature
Tch 150
Storage temperature
Tstg –55 to +150
Notes: 1. When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW ≤ 10s
2. Tch = 25C, Rg 50
3. It provides by the current limitation lower bound value.
(Ta = 25°C)
Unit
V
V
V
A
A
A
mJ
W
C
C
R07DS0874EJ0100 Rev.1.00
Aug 29, 2012
Page 1 of 7
1 page  
RJF0613JSP
Target Specifications
Gate to Source Voltage vs.
Shutdown Time of Load-Short Test
16
14
12
10
8
6
24 V
VDD = 16 V
4
2
0
10
100
1000
10000
Shutdown Time of Load-Short Test Pw (μs)
Shutdown Case Temperature vs.
Gate to Source Voltage
200
180
160
140
120 ID = 0.5 A
100
0 2 4 6 8 10
Gate to Source Voltage VGS (V)
Normalized Transient Thermal Impedance vs. Pulse Width
10
1 D=1
0.5
0.2
0.1
0.1
0.05
0.01
0.02
0.01
1shot pulse
0.001
100 μ
1m
θch − f(t) = γs (t) • θch − f
θch − f = 83.3°C/W, Ta = 25°C
When using the glass epoxy board
(FR4 40 × 40 × 1.6 mm)
PDM
D=
PW
T
PW
T
10 m
100 m
1
10
Pulse Width PW (S)
100 1000 10000
R07DS0874EJ0100 Rev.1.00
Aug 29, 2012
Page 5 of 7
5 Page | ||
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