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PDF LTC1608 Data sheet ( Hoja de datos )
| Número de pieza | LTC1608 | |
| Descripción | Sampling A/D Converter | |
| Fabricantes | Linear | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC1608 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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LTC1608
High Speed, 16-Bit, 500ksps
Sampling A/D Converter
with Shutdown
FEATURES
s A Complete, 500ksps 16-Bit ADC
s 90dB S/(N+D) and –100dB THD (Typ)
s Power Dissipation: 270mW (Typ)
s No Pipeline Delay
s No Missing Codes Over Temperature
s Nap (7mW) and Sleep (10µW) Shutdown Modes
s Operates with Internal 15ppm/°C Reference
or External Reference
s True Differential Inputs Reject Common Mode Noise
s 5MHz Full Power Bandwidth
s ±2.5V Bipolar Input Range
s 36-Pin SSOP Package
s Pin Compatible with the LTC1604
U
APPLICATIO S
s Telecommunications
s Digital Signal Processing
s Multiplexed Data Acquisition Systems
s High Speed Data Acquisition
s Spectrum Analysis
s Imaging Systems
DESCRIPTIO
The LTC®1608 is a 500ksps, 16-bit sampling A/D con-
verter that draws only 270mW from ±5V supplies. This
high performance device includes a high dynamic range
sample-and-hold, a precision reference and a high speed
parallel output. Two digitally selectable power shutdown
modes provide power savings for low power systems.
The LTC1608’s full-scale input range is ± 2.5V. Outstand-
ing AC performance includes 90dB S/(N+D) and – 100dB
THD at a sample rate of 500ksps.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 15MHz
bandwidth. The 68dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
The ADC has µP compatible,16-bit parallel output port.
There is no pipeline delay in conversion results. A separate
convert start input and a data ready signal (BUSY) ease
connections to FlFOs, DSPs and microprocessors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Circuitry in the LTC1608 is covered under US Patent #5,764,175
TYPICAL APPLICATIO
+
22µF
DIFFERENTIAL
ANALOG INPUT
± 2.5V
2.2µF
3
VREF
10µF
5V 10µF
10Ω
+
36
+
35
AVDD AVDD
LTC1608
4 REFCOMP
1.75X
7.5k 2.5V
REF
5V 10µF
+
9 10
DVDD
DGND
SHDN 33
CONTROL
LOGIC
AND
TIMING
CS 32
CONVST 31
RD 30
BUSY 27
µP
CONTROL
LINES
1 AIN+
2 AIN–
+
16-BIT
SAMPLING
– ADC
B15 TO B0
OUTPUT
BUFFERS
AGND AGND AGND AGND VSS
5 6 7 8 34
OVDD 29
OGND 28
5V OR
3V
10µF
D15 TO D0
16-BIT
PARALLEL
BUS
11 TO 26
1608 TA01
+ 10µF
–5V
LTC1608 4096 Point FFT
0
fSAMPLE = 500kHz
–20
fIN = 98.754kHz
SINAD = 86.7dB
THD = –92.6dB
–40
–60
–80
–100
–120
–140
0
50 100 150 200
FREQUENCY (kHz)
250
1608 TA02
1
1 page  
LTC1608
ELECTRICAL CHARACTERISTICS
Note 4: When these pin voltages are taken below VSS, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = – 5V, fSMPL = 500kHz, and tr = tf = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specification apply for a single-
ended AIN+ input with AIN– grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Typical RMS noise at the code transitions.
Note 9: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111.
Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion
is measured at 100kHz. These results are used to calculate Signal-to-Nosie
Plus Distortion (SINAD).
Note 11: Guaranteed by design, not subject to test.
Note 12: Recommended operating conditions.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best performance ensure that CONVST returns high either within 250ns
after conversion start or after BUSY rises.
Note 14: The acquisition time would go up to 400ns and the conversion
time would go up to 1.8µs. However, the throughput time (acquisition +
conversion) is guaranteed by test to be 2µs max.
Note 15: If RD↓ precedes CS↓, the output enable will be gated by CS↓.
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity
vs Output Code
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–32768 –16384
0
CODE
16384 32767
1608 G01
Signal-to-Noise Ratio
vs Input Frequency
100
90
80
70
60
50
40
30
20
10
0
1k 10k 100k
FREQUENCY (Hz)
1M
1608 G04
Differential Nonlinearity
vs Output Code
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–32768 –16384
0
CODE
16384 32767
1608 G02
Distortion vs Input Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
1k
THD
3RD
2ND
10k 100k
INPUT FREQUENCY (Hz)
1M
1608 G05
S/(N + D) vs Input Frequency
and Amplitude
100
VIN = 0dB
90
80
VIN = –20dB
70
60
VIN = –40dB
50
40
30
20
10
0
1k 10k 100k 1M
FREQUENCY (Hz)
1608 G03
Spurious-Free Dynamic Range
vs Input Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
1k
10k 100k
INPUT FREQUENCY (Hz)
1M
1608 G06
5
5 Page 
APPLICATIO S I FOR ATIO
CS = 0
RD = CONVST
BUSY
DATA
tCONV
t6
t10
DATA (N – 1)
D15 TO D0
t8
t11
t7
DATA N
D15 TO D0
DATA N
D15 TO D0
Figure 8. Mode 2. Slow Memory Mode Timing
LTC1608
DATA (N + 1)
D15 TO D0
1608 F08
CS = 0
RD = CONVST
BUSY
DATA
tCONV
t6 t11
t10
DATA (N – 1)
D15 TO D0
t8
DATA N
D15 TO D0
1608 F09
Figure 9. ROM Mode Timing
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1608
inputs can be driven directly. As source impedance in-
creases so will acquisition time (see Figure 10). For
minimum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
starts (settling time must be 200ns for full throughput
rate).
10
1
0.1
0.01
1
10 100 1k
SOURCE RESISTANCE (Ω)
10k
1608 F10
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
low output impedance (< 100Ω) at the closed-loop band-
width frequency. For example, if an amplifier is used in a
gain of +1 and has a unity-gain bandwidth of 50MHz, then
Figure 10. tACQ vs Source Resistance
the output impedance at 50MHz should be less than
100Ω. The second requirement is that the closed-loop
bandwidth must be greater than 15MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC1608.PDF ] | |
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