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부품번호 7512 기능
기능 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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7512 데이터시트, 핀배열, 회로
7512 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0122-0101
Rev.1.01
Feb 18, 2005
DESCRIPTION
The 7512 Group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 7512 Group is designed for battery-pack and includes serial
interface functions, 8-bit timer, A/D converter, current integrator
and I2C-BUS interface.
FEATURES
qBasic machine-language instructions ...................................... 71
qMinimum instruction execution time .................................. 1.0 µs
(at 4 MHz oscillation frequency)
qMemory size
Flash memory .................................................. 36 K to 52 Kbytes
RAM ............................................................... 1.0 K to 1.5 Kbytes
qProgrammable input/output ports ............................................ 36
qInterrupts ................................................. 19 sources, 16 vectors
qTimers ............................................................................. 8-bit 4
qSerial interface
Serial I/O1 .......... 8-bit 1 (UART or Clock-synchronized)
Serial I/O2 .......................... 8-bit 1(Clock-synchronized)
qMulti-master I2C-BUS interface (option) ...................... 1 channel
qPWM ............................................................................... 8-bit 1
qA/D converter ............................................. 10-bit 10 channels
qCurrent integrator ......................................................... 1 channel
qOver current detector ................................................... 1 channel
qEasy thermal sensor .................................................... 1 channel
qWatchdog timer ............................................................ 16-bit 1
qClock generating circuit ..................................... Built-in 4 circuits
(high-speed RC oscillator and 32kHz RC oscillator, or connect to
external ceramic resonator or quartz-crystal oscillator)
qPower source voltage ............................................ 2.45 to 2.55 V
qPower dissipation
In high-speed mode ...................................................... 3.75 mW
(at 4 MHz oscillation frequency, at 2.5 V power source voltage)
In low-speed mode ........................................................ 1.05 mW
(at 32 kHz oscillation frequency, at 2.5 V power source voltage)
qOperating temperature range .................................... –20 to 85°C
APPLICATION
Battery-Pack, etc.
PIN CONFIGURATION (TOP VIEW)
P33/AN3
P32/AN2
P31/AN1
P30/AN0
ADVSS
ADVRED
VCC
AVCC
AVSS
ISENS0
ISENS1
DFETCNT/P45
37
38
39
40
41
42
43
44
45
46
47
48
M37512FCHP
24 P12/(LED2)
23 P13/(LED3)
22 P14/(LED4)
21 P15/(LED5)
20 P16/(LED6)
19 P17/(LED7)
18 VSS
17 XOUT
16 XIN
15 RESET
14 P20/XCOUT
13 P21/XCIN
Fig. 1 M37512FCHP pin configuration
Feb 18, 2005 page 1 of 85
REJ03B0122-0101
Package type : 48P6Q-A




7512 pdf, 반도체, 판매, 대치품
7512 Group
GROUP EXPANSION
Renesas plans to expand the 7512 group as follows.
Memory Type
Support for flash memory version.
Memory Expansion Plan
ROM size (bytes)
60K
Memory Size
ROM size ........................................................... 36 K to 52 K bytes
RAM size .......................................................... 1024 to 1536 bytes
Packages
48P6Q-A ............................................... 48-pin plastic molded QFP
48K
32K
Mass production
M37512FC
Under development
M37512FCH
Mass production
Under development
M37512F8
M37512F8H
Fig. 3 Memory expansion plan
768
1024
1280
RAM size (bytes)
1536
3072
Currently planning products are listed below.
Table 2 Support products
Product name
ROM size (bytes)
RAM size (bytes) Package
Remarks
M37512F8HP
M37512F8-XXXHP
M37512F8HHP
(Note 1)
32K + 4K
1024
M37512F8H-XXXHP (Note 1)
M37512FCHP
48P6Q-A
M37512FC-XXXHP
M37512FCHHP
(Note 1)
48K + 4K
1536
M37512FCH-XXXHP (Note 1)
Note 1. The products of which erase/write cycles onto the blocks A and B are maximum 10k are under development.
Feb 18, 2005 page 4 of 85
REJ03B0122-0101

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7512 전자부품, 판매, 대치품
7512 Group
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is 0, and cleared if the result is anything other
than 0.
Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is 1.
Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is 0; decimal arithmetic is executed when it is 1.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can execute decimal arithmetic.
Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always 0. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to 1.
Bit 5: Index X mode flag (T)
When the T flag is 0, arithmetic operations are performed
between accumulator and memory. When the T flag is 1, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 4 Set and clear instructions of each bit of processor status register
C flag
Z flag
I flag
D flag
Set instruction
SEC
SEI SED
Clear instruction
CLC
CLI CLD
B flag
T flag
SET
CLT
V flag
CLV
N flag
Feb 18, 2005 page 7 of 85
REJ03B0122-0101

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