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M301N2F8TFP 데이터시트 PDF




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부품번호 M301N2F8TFP 기능
기능 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
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M301N2F8TFP 데이터시트, 핀배열, 회로
M16C/1N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0002-0100Z
Rev.1.00
2004.10.20
1. Overview
The M16C/1N group consists of single-chip microcomputers that use high-performance silicon gate CMOS
processes and have a on-chip M16C/60 series CPU core. The microcomputers are housed in 48-pin plastic
mold QFP package. These single-chip microcomputers have both high function instructions and high in-
struction efficiency and feature a one-megabyte address space and the capability to execute instructions at
high speed.
1.1 Applications
Automotive and industrial control systems, other automobile, other
Rev.1.00 Oct 20, 2004 page 1 of 29
REJ03B0002-0100Z




M301N2F8TFP pdf, 반도체, 판매, 대치품
M16C/1N Group
1.4 Performance Overview
Table 1.2 shows performance overview.
Table 1.2 Performance overview
Type No.
M301N2M4T-XXXFP(D)
M301N2M8T-XXXFP(D)
M301N2F8TFP(D)
M301N2F8FP(D)
(D): Under development
ROM
32Kbytes
64Kbytes
RAM
1Kbytes
3Kbytes
1. Overview
Package
48P6Q-A
As of June 2004
Remarks
Mask ROM
Flash memory
Type No. M30 1N 2 M 4 T - XXX FP
Package type:
FP: Package 48P6Q-A
ROM No.
Omitted for flash memory version
Indicates differences in characteristics and usage etc:
Nothing: Common
T: Automobiles
ROM size:
4: 32 Kbytes
8: 64 Kbytes
Memory type:
M: Mask ROM version
F: Flash memory version
Indicates pin count, etc
(The value itself has no specific meaning)
M16C/1N Group
M16C Family
Figure 1.2 Type No., memory size, and package
Rev.1.00 Oct 20, 2004 page 4 of 29
REJ03B0002-0100Z

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M301N2F8TFP 전자부품, 판매, 대치품
M16C/1N Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
R2
R3
b15 b8 b7
b0
R0H (R0's high bits) R0L (R0's low bits)
R1H (R1's high bits) R1L (R1's low bits)
R2
R3
A0
A1
FB
Data registers (Note 1)
Address registers (Note 1)
Frame base registers (Note 1)
b19
INTBH
INTBL
b0
Interrupt table register
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19
PC
b0
Program counter
b15
USP
ISP
SB
b0
User stack pointer
Interrupt stack pointer
Static base register
b15
IPL
b15
FLG
b0
b8 b7
b0
U I OBSZ DC
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note 1: These registers comprise a register bank. There are two register banks.
Figure 2.1 CPU Registers
2.1 Data Registers (R0, R1, R2, and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The A0 register consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev.1.00 Oct 20, 2004 page 7 of 29
REJ03B0002-0100Z

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