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PDF LTC2336-18 Data sheet ( Hoja de datos )
| Número de pieza | LTC2336-18 | |
| Descripción | Fully Differential Input ADC | |
| Fabricantes | Linear | |
| Logotipo |  |
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Features
LTC2336-18
18-Bit, 250ksps, ±10.24V
True Bipolar, Fully Differential
Input ADC with 100dB SNR
Description
n 250ksps Throughput Rate
n ±4LSB INL (Max)
n Guaranteed 18-Bit No Missing Codes
n Fully Differential Inputs
n True Bipolar Input Ranges ±6.25V, ±10.24V, ±12.5V
n 100dB SNR (Typ) at fIN = 2kHz
n –115dB THD (Typ) at fIN = 2kHz
n Guaranteed Operation to 125°C
n Single 5V Supply
n Low Drift (20ppm/°C Max) 2.048V Internal Reference
n Onboard Single-Shot Capable Reference Buffer
n No Pipeline Delay, No Cycle Latency
n 1.8V to 5V I/O Voltages
n SPI-Compatible Serial I/O with Daisy-Chain Mode
n Internal Conversion Clock
n Power Dissipation 28mW (Typ)
n 16-Lead MSOP Package
Applications
n Programmable Logic Controllers
n Industrial Process Control
n High Speed Data Acquisition
n Portable or Compact Instrumentation
n ATE
The LTC®2336-18 is a low noise, high speed 18-bit succes-
siveapproximation register(SAR)ADCwithfullydifferential
inputs. Operating from a single 5V supply, the LTC2336-18
has a ±10.24V true bipolar input range, making it ideal for
high voltage applications which require a wide dynamic
range. The LTC2336-18 achieves ±4LSB INL maximum,
no missing codes at 18-bits with 100dB SNR.
The LTC2336-18 has an onboard single-shot capable
reference buffer and low drift (20ppm/°C max) 2.048V
temperature compensated reference. The LTC2336-18
also has a high speed SPI-compatible serial interface that
supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring
a daisy-chain mode. The fast 250ksps throughput with
no cycle latency makes the LTC2336-18 ideally suited
for a wide variety of high speed applications. An internal
oscillator sets the conversion time, easing external timing
considerations. The LTC2336-18 dissipates only 28mW
and automatically naps between conversions, leading to
reduced power dissipation that scales with the sampling
rate. A sleep mode is also provided to reduce the power
consumption of the LTC2336-18 to 300μW for further
power savings during inactive periods.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 7705765 and 7961132
Typical Application
+10.24V
–10.24V
+10.24V
–10.24V
+
–
5V
10µF
1.8V TO 5V
2.2µF
0.1µF
VDD
IN+
VDDLBYP OVDD
LTC2336-18
IN–
RERFEBFUF
REFIN
GND
47µF
100nF
CHAIN
RDL/SDI
SDO
SCK
BUSY
CNV
233618 TA01
SAMPLE CLOCK
For more information www.linear.com/LTC2336-18
32k Point FFT fS = 250ksps,
fIN = 2kHz
0 SNR = 100.3dB
–20 THD = –117dB
SINAD = 100.2dB
–40 SFDR = –118dB
–60
–80
–100
–120
–140
–160
–180
0
25 50 75 100 125
FREQUENCY (kHz)
233618 TA01b
233618f
1
1 page  
LTC2336-18
A DC Timing Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fSMPL
tCONV
tACQ
tHOLD
tCYC
tCNVH
tBUSYLH
tCNVL
tQUIET
Maximum Sampling Frequency
Conversion Time
Acquisition Time
Maximum Time between Acquisitions
Time Between Conversions
CNV High Time
CNV↑ to BUSY Delay
Minimum Low Time for CNV
SCK Quiet Time from CNV↑
tACQ = tCYC – tHOLD (Note 11)
CL = 20pF
(Note 12)
(Note 11)
l
l 1.9
l 3.460
l
l4
l 20
l
l 20
l 20
250 ksps
3 µs
µs
540 ns
µs
ns
13 ns
ns
ns
tSCK
tSCKH
tSCKL
tSSDISCK
SCK Period
SCK High Time
SCK Low Time
SDI Setup Time From SCK↑
(Notes 12, 13)
(Note 12)
l 10
l4
l4
l4
ns
ns
ns
ns
tHSDISCK
tSCKCH
tDSDO
tHSDO
SDI Hold Time From SCK↑
SCK Period in Chain Mode
SDO Data Valid Delay from SCK↑
SDO Data Remains Valid Delay from SCK↑
(Note 12)
tSCKCH = tSSDISCK + tDSDO (Note 12)
CL = 20pF, OVDD = 5.25V
CCLL
=
=
20pF,
20pF,
OOVVDDDD
=
=
2.5V
1.71V
CL = 20pF (Note 11)
l1
l 13.5
l
l
l
l1
ns
ns
7.5 ns
8 ns
9.5 ns
ns
tDSDOBUSYL
tEN
SDO Data Valid Delay from BUSY↓
Bus Enable Time After RDL↓
CL = 20pF (Note 11)
(Note 12)
l 5 ns
l 16 ns
tDIS Bus Relinquish Time After RDL↑
(Note 12)
l 13 ns
tWAKE
REFBUF Wakeup Time
CREFBUF = 47μF, CREFIN = 100nF
200 ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above VDD or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above VDD or OVDD without
latch-up.
Note 4: VDD = 5V, OVDD = 2.5V, ±10.24V Range, REFIN = 2.048V,
fSMPL = 250kHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 00 0000 0000 0000 0000 and 11
1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS
or +FS untrimmed deviation from ideal first and last code transitions and
includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±20.48V input
with REFIN = 2.048V.
Note 9: When REFBUF is overdriven, the internal reference buffer must be
turned off by setting REFIN = 0V.
Note 10: fSMPL = 250kHz, IREFBUF varies proportionally with sample rate.
Note 11: Guaranteed by design, not subject to test.
Note 12: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 13: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising edge capture.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
0.8 • OVDD
tDELAY
0.2 • OVDD
tDELAY
50%
tWIDTH
0.8 • OVDD
0.2 • OVDD
0.8 • OVDD
0.2 • OVDD
Figure 1. Voltage Levels for Timing Specifications
50%
233618 F01
For more information www.linear.com/LTC2336-18
233618f
5
5 Page 
LTC2336-18
Applications Information
the output of the resistor divider network. Any unwanted
signal that is common to both inputs will be reduced by
the common mode rejection of the ADC core and resistor
divider network. The inputs of the ADC core draw a current
spike while charging the CIN capacitors during acquisition.
Input Drive Circuits
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
A low impedance source can directly drive the high im-
pedance inputs of the LTC2336-18 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the dis-
tortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC inputs
draw a current spike when entering acquisition.
For best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2336-18. The amplifier
provides low output impedance to minimize gain error
and allows for fast settling of the analog signal during
the acquisition phase. It also provides isolation between
the signal source and the ADC inputs which draw a small
current spike during acquisition.
Input Filtering
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with a low bandwidth filter to
minimize noise. The simple 1-pole RC lowpass filter shown
in Figure 4 is sufficient for many applications.
The input resistor divider network, sampling switch on-
resistance (RON) and the sample capacitor (CIN) form a
second lowpass filter that limits the input bandwidth to
the ADC core to 7MHz. A buffer amplifier with a low noise
density must be selected to minimize the degradation of
the SNR over this bandwidth.
Single-Ended-to-Differential Conversion
For single-ended input signals, a single-ended-to-differen-
tial conversion circuit must be used to produce a differential
signal at the inputs of the LTC2336-18. The LT1469 high
speed dual operational amplifier is recommended for per-
forming single-ended-to-differential conversions as shown
in Figure 5a. In this case, the first amplifier is configured
as a unity gain buffer and the single-ended input signal
directly drives the high impedance input of this amplifier.
Figure 5b shows the resulting FFT when the LT1469 is used
to drive the LTC2336-18 in this configuration.
±10.24V
LT1469
3+
2–
5+
6–
4.99k 4.99k
1 OUT1
±10.24V
7 OUT2
±10.24V
233618 F05a
Figure 5a. LT1469 Converting a ±10.24V Single-Ended
Signal to a ±20.48V Differential Input Signal
0
–20
–40
–60
–80
–100
SNR = 100dB
THD = –115dB
SINAD = 99.9dB
SFDR = –118dB
SINGLE-ENDED
INPUT SIGNAL
500Ω
6600pF
IN+
LTC2336-18
IN–
BW = 48kHz
SINGLE-ENDED-
TO-DIFFERENTIAL
DRIVER
Figure 4. Input Signal Chain
233618 F04
–120
–140
–160
–180
0
25 50 75 100 125
FREQUENCY (kHz)
233618 F05b
Figure 5b.
for Circuit
128k Point FFT Plot
Shown in Figure 5a
with
fIN
=
2kHz
233618f
For more information www.linear.com/LTC2336-18
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC2336-18.PDF ] | |
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