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PDF LTC2446 Data sheet ( Hoja de datos )
| Número de pieza | LTC2446 | |
| Descripción | 24-Bit High Speed 8-Channel ADCs | |
| Fabricantes | Linear | |
| Logotipo |  |
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LTC2446/LTC2447
24-Bit High Speed
8-Channel ∆Σ ADCs with
Selectable Multiple Reference Inputs
FEATURES
■ Five Selectable Differential Reference Inputs
■ Four Differential/Eight Single-Ended Inputs
■ 4-Way MUX for Multiple Ratiometric
Measurements
■ Up to 8kHz Output Rate
■ Up to 4kHz Multiplexing Rate
■ Selectable Speed/Resolution:
2µVRMS Noise at 1.76kHz Output Rate
200nVRMS Noise at 13.8Hz Output Rate with
Simultaneous 50/60Hz Rejection
■ Guaranteed Modulator Stability and Lock-Up
Immunity for any Input and Reference Conditions
■ 0.0005% INL, No Missing Codes
■ Autosleep Enables 20µA Operation at 6.9Hz
■ < 5µV Offset (4.5V < VCC < 5.5V, – 40°C to 85°C)
■ Differential Input and Differential Reference with
GND to VCC Common Mode Range
■ No Latency Mode, Each Conversion is Accurate Even
After a New Channel is Selected
■ Internal Oscillator—No External Components
■ LTC2447 Includes MUXOUT/ADCIN for External
Buffering or Gain
■ Tiny QFN 5mm x 7mm Package
U
APPLICATIO S
■ Flow
■ Weight Scales
■ Pressure
■ Direct Temperature Measurement
■ Gas Chromatography
DESCRIPTIO
The LTC®2446/LTC2447 4-terminal switching enables
multiplexed ratiometric measurements. Four sets of se-
lectable differential inputs coupled with four sets of differ-
ential reference inputs allow multiple RTDs, bridges and
other sensors to be digitized by a single converter. A fifth
differential reference input can be selected for any input
channel not requiring ratiometric measurements (ther-
mocouples, voltages, current sense, etc.). The flexible
input multiplexer allows single-ended or differential in-
puts coupled with a slaved reference input or a universal
reference input.
A proprietary delta-sigma architecture results in absolute
accuracy (offset, full-scale, linearity) of 15ppm, noise as
low as 200nVRMS and speeds as high as 8kHz. Through a
simple 4-wire interface, ten speed/resolution combina-
tions can be selected. The first conversion following a
speed, resolution, channel change or reference change is
valid since there is no settling time between conversions,
enabling scan rates of up to 4kHz. Additionally, a 2x mode
can be selected for any speed-enabling output rates up to
8kHz with one cycle of latency.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Protected by U.S. Patents, including 6140950, 6169506, 6208279, 6411242, 6639526
TYPICAL APPLICATIO
Multiple Ratiometric Measurement System
VCC
REF+
LTC2446
•
•
•
IN+
19-INPUT
4-OUTPUT
+
VARIABLE SPEED/
RESOLUTION 24-BIT
MUX IN– – ∆Σ ADC
REF–
CS
SDI
SDO
SCK
24467 TA01
LTC2446 Speed vs RMS Noise
100
VCC = 5V
VVRINE+F
=
=
5V
VIN–
=
0V
2x SPEED MODE
NO LATENCY MODE
10
2.8µV AT 880Hz
280nV AT 6.9Hz
1 (50/60Hz REJECTION)
0.1
1
10 100 1000
CONVERSION RATE (Hz)
10000
24467 TA02
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1 page  
LTC2446/LTC2447
TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
DISCK
fESCK
Internal SCK Duty Cycle
External SCK Frequency Range
(Note 9)
(Note 8)
● 45
●
55 %
20 MHz
tLESCK
tHESCK
External SCK Low Period
External SCK High Period
(Note 8)
(Note 8)
● 25
● 25
ns
ns
tDOUT_ISCK
tDOUT_ESCK
t1
Internal SCK 32-Bit Data Output Time
External SCK 32-Bit Data Output Time
CS ↓ to SDO Low Z
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
(Note 8)
(Note 12)
● 41.6
35.3 30.9
● 320/fEOSC
● 32/fESCK
●0
25
µs
s
s
ns
t2 CS ↑ to SDO High Z
t3 CS ↓ to SCK ↓
(Note 12)
(Note 9)
●0
25
5
ns
µs
t4
tKQMAX
CS ↓ to SCK ↑
SCK ↓ to SDO Valid
(Notes 8, 12)
● 25
●
ns
25 ns
tKQMIN
t5
SDO Hold After SCK ↓
SCK Setup Before CS ↓
(Note 5)
● 15
● 50
ns
ns
t6 SCK Hold After CS ↓
t7 SDI Setup Before SCK ↑
(Note 5)
●
● 10
50 ns
ns
t8 SDI Hold After SCK ↑
(Note 5)
● 10
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 4.5V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; REF+ is the positive
reference input, REF– is the negative reference input; VIN = IN+ – IN–,
VINCM = (IN+ + IN–)/2.
Note 4: FO pin tied to GND or to external conversion clock source with
fEOSC = 10MHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: The converter uses the internal oscillator.
Note 8: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 9: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output. In this mode of operation, the SCK pin
has a total equivalent load capacitance of CLOAD = 20pF.
Note 10: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in Hz.
Note 11: The converter uses the internal oscillator. FO = 0V.
Note 12: Guaranteed by design and test correlation.
Note 13: There is an internal reset that adds an additional 1µs (typ) to the
conversion time.
PI FU CTIO S
GND (Pins 1, 4, 5, 6, 31, 32, 33): Ground. Multiple
ground pins internally connected for optimum ground
current flow and VCC decoupling. Connect each one of
these pins to a common ground plane through a low
impedance connection. All seven pins must be connected
to ground for proper operation.
BUSY (Pin 2): Conversion in Progress Indicator. This pin
is HIGH while the conversion is in progress and goes LOW
indicating the conversion is complete and data is ready. It
remains LOW during the sleep and data output states. At
the conclusion of the data output state, it goes HIGH
indicating a new conversion has begun.
EXT (Pin 3): Internal/External SCK Selection Pin. This pin
is used to select internal or external SCK for outputting/
inputting data. If EXT is tied low, the device is in the
external SCK mode and data is shifted out of the device
under the control of a user applied serial clock. If EXT is
tied high, the internal serial clock mode is selected. The
device generates its own SCK signal and outputs this on
the SCK pin. A framing signal BUSY (Pin 2) goes low
indicating data is being output.
COM (Pin 7): The common negative input (IN–) for all
single ended multiplexer configurations. The voltage on
CH0-CH7 and COM pins can have any value between GND
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LTC2446/LTC2447
APPLICATIO S I FOR ATIO
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 38) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2446/LTC2447 create their own serial
clock. In the External SCK mode of operation, the SCK pin
is used as input. The internal or external SCK mode is
selected by tying EXT (Pin 3) LOW for external SCK and
HIGH for internal SCK.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 37), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 36) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 36), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2446/LTC2447 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CS pin after the converter has entered the data output
state.
Serial Data Input (SDI)
The serial data input (SDI, Pin 34) is used to select the
speed/resolution input channel and reference of the
LTC2446/LTC2447. SDI is programmed by a serial input
data stream under the control of SCK during the data
output cycle, see Figure 3.
Initially, after powering up, the device performs a conver-
sion with IN+ = CH0, IN– = CH1, REF+ = VREF01+, REF– =
VREF01–, OSR = 256 (output rate nominally 880Hz), and 1x
speed mode (no Latency). Once this first conversion is
complete, the device enters the sleep state and is ready to
output the conversion result and receive the serial data input
stream programming the speed/resolution, input channel
and reference for the next conversion. At the conclusion of
each conversion cycle, the device enters this state.
In order to change the speed/resolution, reference or input
channel, the first 3 bits shifted into the device are 101. This
is compatible with the programming sequence of the
LTC2414/LTC2418/LTC2444/LTC2445/LTC2448/
LTC2449. If the sequence is set to 000 or 100, the follow-
ing input data is ignored (don’t care) and the previously
selected speed/resolution, channel and reference remain
valid for the next conversion. Combinations other than 101,
100, and 000 of the 3 control bits should be avoided.
If the first 3 bits shifted into the device are 101, then the
following 5 bits select the input channel/reference for the
following conversion (see Table 3). The next 5 bits select
the speed/resolution and mode 1x (no Latency) 2x (double
output rate with one conversion latency), see Table 4. If
these 5 bits are set to all 0’s, the previous speed remains
selected for the next conversion. This is useful in applica-
tions requiring a fixed output rate/resolution but need to
change the input channel or reference. In this case, the
timing and input sequence is compatible with the LTC2414/
LTC2418.
When an update operation is initiated (the first 3 bits are
101) the next 5 bits are the channel/reference address. The
first bit, SGL, determines if the input selection is differen-
tial (SGL = 0) or single-ended (SGL = 1). For SGL = 0, two
adjacent channels can be selected to form a differential
input. For SGL = 1, one of 8 channels is selected as the
positive input. The negative input is COM for all single
ended operations. The global VREF bit (GLBL) is used to
determine which reference is selected. GLBL = 0 selects
the individual reference slaved to a given channel. Each set
of channels has a corresponding differential input refer-
ence. If GLBL = 1, a global reference VREFG+/VREFG– is
selected. The global reference input may be used for any
input channel selected. Table 3 shows a summary of input/
reference selection. The remaining bits (ODD, A1, A0)
determine which channel is selected.
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11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC2446.PDF ] | |
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