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PDF AD8285 Data sheet ( Hoja de datos )
| Número de pieza | AD8285 | |
| Descripción | 4-Channel LNA/PGA/AAF | |
| Fabricantes | Analog Devices | |
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Data Sheet
Radar Receive Path AFE: 4-Channel
LNA/PGA/AAF with ADC
AD8285
FEATURES
4-channel LNA, PGA, and AAF
1 direct to ADC channel
Programmable gain amplifier (PGA)
Includes low noise preamplifier (LNA)
Serial peripheral interface (SPI) programmable gain
16 dB to 34 dB in 6 dB steps
Antialiasing filter (AAF)
Programmable third order, low-pass elliptic filter (LPF)
from 1.0 MHz to 12.0 MHz
Analog-to-digital converter (ADC)
12 bits of accuracy up to 72 MSPS
Signal-to-noise ratio (SNR): 68.5 dB
Spurious-free dynamic range (SFDR): 68 dB at gain = 16 dB
Low power: 185 mW per channel at 12 bits and 72 MSPS
Low noise: 3.5 nV/√Hz maximum of input referred voltage noise
Power-down mode
72-lead, 10 mm × 10 mm LFCSP package
Specified from −40°C to +105°C
Qualified for automotive applications
APPLICATIONS
Automotive radar
Adaptive cruise control
Collision avoidance
Blind spot detection
Self parking
Electronic bumper
FUNCTIONAL BLOCK DIAGRAM
INA+
INA–
INB+
INB–
INC+
INC–
IND+
IND–
INADC+
INADC–
LNA PGA AAF
LNA PGA AAF
LNA PGA AAF
LNA PGA AAF
SPI
REFERENCE
MUX
12-BIT
ADC
DRV
AD8285
DSYNC
D[0:11]
NOTES
1. AVDD18x = AVDD18, AVDD18ADC.
AVDD33x = AVDD33, AVDD33A, AVDD33B, AVDD33C, AVDD33D, AVDD33REF.
DVDD18x = DVDD18, DVDD18CLK. DVDD33x = DVDD33, DVDD33SPI, DVDD33CLK, DVDD33DRV.
Figure 1.
GENERAL DESCRIPTION
The AD8285 is designed for low cost, low power, compact size,
flexibility, and ease of use. It contains four channels of a low noise
preamplifier (LNA) with a programmable gain amplifier (PGA)
and an antialiasing filter (AAF) plus one direct to ADC channel, all
integrated with a single 12-bit analog-to-digital converter (ADC).
Each channel features a gain range of 16 dB to 34 dB in 6 dB
increments and an ADC with a conversion rate of up to 72 MSPS.
The combined input referred noise voltage of the entire channel
is 3.5 nV/√Hz at maximum gain. The channel is optimized for
dynamic performance and low power in applications where a
small package size is critical.
Fabricated in an advanced complementary metal oxide
semiconductor (CMOS) process, the AD8285 is available in a
10 mm × 10 mm, RoHS compliant, 72-lead LFCSP that is specified
over the automotive temperature range of −40°C to +105°C.
Table 1. Related Devices
Part No. Description
AD8283 6-channel LNA/PGA/AAF, pseudo simultaneous
channel sampling with ADC
AD8284 4-channel LNA/PGA/AAF, sequential channel
sampling with ADC
ADA8282 4-channel LNA/PGA
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rights of thirdpartiesthatmay result fromits use. Specificationssubject tochangewithout notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices.Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD8285
DIGITAL SPECIFICATIONS
AVDD18 = AVDD18ADC = 1.8 V, AVDD33 = AVDD33x1 = AVDD33REF = 3.3 V, DVDD18 = DVDD18CLK = 1.8 V, DVDD33SPI =
DVDD33CLK = DVDD33DRV = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain =
34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted.
Table 3.
Parameter2
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage3
Input Common-Mode Voltage
Differential Input Resistance
Input Capacitance
LOGIC INPUTS (PDWN, SCLK, AUX, MUXA, ZSEL)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CS)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO)4
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
LOGIC OUTPUT (Dx, DSYNC)
Logic 1 Voltage (IOH = 2 mA)
Logic 0 Voltage (IOL = 2 mA)
Temperature
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Min
250
1.2
1.2
1.2
0
3.0
3.0
Typ Max
Unit
CMOS/LVDS/LVPECL
1.2
20
1.5
mV p-p
V
kΩ
pF
3.6
0.3
30
0.5
V
V
kΩ
pF
3.6
0.3
70
0.5
V
V
kΩ
pF
DVDD33x + 0.3 V
0.3 V
30 kΩ
2 pF
V
0.3 V
V
0.05 V
1 x stands for A, B, C, or D.
2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions, and how these tests were completed.
3 Specified for LVDS and LVPECL only.
4 Specified for 13 SDIO pins sharing the same connection.
Rev. B | Page 5 of 27
5 Page 
Data Sheet
12000
10000
8000
6000
4000
2000
0
–7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7
CODE
Figure 10. Output Referred Noise Histogram (Gain = 16 dB)
7000
6000
5000
4000
3000
2000
1000
0 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7
CODE
Figure 11. Output Referred Noise Histogram (Gain = 34 dB)
15
10
16dB
5
22dB
28dB
34dB
0
0.1 1 10
FREQUENCY (MHz)
Figure 12. Short-Circuit Input Referred Noise vs. Frequency
AD8285
70
SNR
65
SINAD
60
55
50
45
40
16
22 28
GAIN (dB)
Figure 13. SNR/SINAD vs. Gain
34
20
10
0
–10
–20
–30
–40
–50
0.1
12MHz
8MHz
4MHz
2MHz
1MHz
1 10
FREQUENCY (Hz)
Figure 14. Filter Response
100
200
180
160
34dB
140
120
100
28dB
80
22dB
60
16dB
40
20
0
0.1 1 10
FREQUENCY (MHz)
Figure 15. Short-Circuit Output Referred Noise vs. Frequency
Rev. B | Page 11 of 27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet AD8285.PDF ] | |
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