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PDF LTC1840 Data sheet ( Hoja de datos )
| Número de pieza | LTC1840 | |
| Descripción | Dual Fan Controller | |
| Fabricantes | Linear | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC1840 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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FEATURES
s Two 8-Bit Current DACs
s DACs Guaranteed Monotonic
s Known IC State on Power-Up
s Serial Interface Watchdog Timer with Disable
s 2-Wire Serial Interface Compatible with I2CTM
and SMBus
s 2 Programmable Fan Tachometer Interfaces
s 4 Programmable General Purpose I/Os
s Small 16-Pin SSOP Package
s Single 2.7V to 5.75V Supply Operation
s Fault Output Signal
s Status Register
s Fan Blasting Function
s Nine Addresses Using Two Programming Lines
U
APPLICATIO S
s Servers
s Desktop Computers
s Power Supplies
s Cooling Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
I2C is a trademark of Philips Electronics N.V.
LTC1840
Dual Fan Controller
with 2-Wire Interface
DESCRIPTIO
The LTC®1840 is a fan controller with two 8-bit current
output DACs, two tachometer interfaces, and four general
purpose I/O (GPIO) pins. It operates from a single supply
with a range of 2.7V to 5.75V. A current output DAC is used
to control an external switching regulator, which controls
the fan speed. A current output DAC and tachometer allow
a controller to form a closed control loop on fan velocity.
The GPIO pins can be used as digital inputs or open drain
pull-down outputs.
The part features a simple 2-wire I2C and SMBus compat-
ible serial interface that allows communication between
many devices. The interface includes a fault status register
that reflects the state of the part and which can be polled
to find the cause of a fault condition. Other operational
characteristics of the part, such as DAC output currents,
GPIO modes, and tachometer frequency, are also pro-
grammed through the serial interface. Two address pins
provide nine possible device addresses.
The BLAST pin is provided to force the DAC output
currents to program the maximum regulator output
voltages through a single pin and gate the operation of the
serial access timer.
TYPICAL APPLICATIO
Low Parts Count, High Efficiency Dual Fan Control
3.3V
3.3V +
10µF
10k VCC
FAULT
GPI04
TO
MASTER
SDA
BLAST
SYSTEM
RESET
SCL IDACOUTA
0.1µF
RC1
10k
CC1
220pF
CFB1
100pF
12V
VIN
RUN/SS SENSE
LTC1771
ITH PGATE
RSENSE1
0.05Ω
VFB MODE
GND
+
CVIN1
22µF
Si6447DQ
L1 47µH
UPS5817
RFB1A
75k +
RFB1B
28k
DC
FAN
COUT1
150µF
3.3V
10k
TACH
OUT
LTC1840
3.3V
3.3V
130Ω
NC
A0
GPI03
130Ω
LED2
LED1 NC A1
IDACOUTB
GPI01
TACHB
GPI02
TACHA
GND
ADDRESS = 1110010
(8 OTHERS POSSIBLE)
RC2
10k
CC2
220pF
CFB2
100pF
12V
VIN
RUN/SS SENSE
LTC1771
ITH PGATE
RSENSE2
0.05Ω
VFB MODE
GND
+
CVIN2
22µF
Si6447DQ
L2 47µH
UPS5817
2-NMB 6820PL-04W-B29-D50 FANS
1.1A NOM AT 12V
3.3V
RFB2A
75k +
RFB2B
28k
DC
FAN
COUT2
150µF
10k
TACH
OUT
1840 TA01
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1
1 page  
TYPICAL PERFOR A CE CHARACTERISTICS
LTC1840
DAC INL at VCC = 3V
0.4
TA = 25°C
0.3
0.2
0.1
0
–0.1
–0.2
0
CODE
255
1840 G10
BLAST Falling Threshold
at VCC = 3V
1.011
1.010
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
–50 –25 0 25 50
TEMPERATURE (°C)
75 100
1840 G11
PI FU CTIO S
SCL (Pin 1): Serial Clock Input. The 2-wire bus master
device clocks this pin at a frequency between 0kHz and
100kHz to enable serial bus communications. Data at the
SDA pin is shifted in or out on rising SCL edges. SCL has
a logic threshold of 1V and an external pull-up resistor or
current source is normally required.
SDA (Pin 2): Serial Data Input. This is a bidirectional data
pin which normally has an external pull-up resistor or
current source and can be pulled down by the open drain
device on the LTC1840 or by external devices. The master
controls SDA during addressing, the writing of data, and
read acknowledgment, while the LTC1840 controls SDA
when data is being read back and during write acknowl-
edgment. SDA data is shifted in or out on rising SCL edges.
SDA has a logic threshold of 1V.
A1 (Pin 3): Three State Address Programming Input. This
pin can cause three different logic states internally, de-
pending upon whether it is pulled to supply, pulled to
ground, or not connected (NC). Combined with the A0 pin,
this provides for nine different possible two-wire bus
addresses for the LTC1840 (see Table 1).
A0 (Pin 4): Three State Address Programming Input. See
A1.
FAULT (Pin 5): Fault Indicator Pull-Down Output. This pin
has an open drain pull-down that is used to signal various
fault conditions on the LTC1840. An external 10k pull-up
is recommended.
GPIO1, GPIO2, GPIO3, GPIO4 (Pins 6, 7, 9, 10): General
Purpose Inputs/Outputs. These pins can be used as digital
inputs with CMOS logic thresholds or digital outputs/LED
drivers with open drain pull-downs that can be pro-
grammed to blink. GPIO pins can be programmed to
produce faults due to changes in their logic states, and
these faults can only be cleared by software or powering
the LTC1840 down. All GPIOs default to nonfaulting logic
inputs upon power-up and their functionality is changed
through the serial interface.
GND (Pin 8): Ground. Connect to analog ground plane.
TACHA (Pin 11): Tachometer Input A. This pin is a digital
input that is designed to interface to the tachometer output
from a 3-wire fan. Internal logic counts between rising
TACHA edges at serially programmable frequencies of
25kHz, 12.5kHz, 6.25kHz or 3.125kHz and the most re-
cently completed count is stored in a register accessible
through the serial interface. The maximum count is 255
and the LTC1840 is programmable to produce faults when
a count exceeds this number. This pin has CMOS thresh-
olds and the default conditions are to count at 3.125kHz
and to not produce faults.
TACHB (Pin 12): Tachometer Input B. See TACHA
1840f
5
5 Page 
U
OPERATIO
VOUT
(5V TO 12V)
REGULATOR
VFB
1.25V
FB
R1
69.8k
LTC1840*
IDAC
IDACOUTA
15(14) (IDACOUTB)
R2
23.2k
1840 F01
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
Figure 1. Feedback Divider for 1.25V Reference
VOUT
BYS10-25
LTC1840
VOUT
(5V TO 12V)
REGULATOR
FB
1.3V
VFB
0.8V
R3
69.8k
LTC1840*
IDAC
IDACOUTA
15(14) (IDACOUTB)
R1
10k
1840 F02
R2
15k *ADDITIONAL DETAILS
OMITTED FOR CLARITY
Figure 2. Feedback Divider for 0.8V Reference
FAN 1
FAN 2
1840 F03
FAN 1, FAN 2: NMB 6820PL-04W-B49-D50
Figure 3. Series Diode to Avoid Beat Frequencies
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
16 15 14 13 12 11 10 9
0.009
(0.229)
REF
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
0.007 – 0.0098
(0.178 – 0.249)
0.015
(0.38
±
±
0.004
0.10)
×
45°
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1 234 5678
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
GN16 (SSOP) 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1840f
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LTC1840.PDF ] | |
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