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부품번호 | JS29F32G08CAMC1 기능 |
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기능 | MD516 NAND Flash Memory | ||
제조업체 | Intel | ||
로고 | |||
전체 30 페이지수
Intel® MD516 NAND Flash Memory
JS29F16G08AAMC1, JS29F32G08CAMC1, JS29F64G08FAMC1
Product Features
Advance Datasheet
Open NAND Flash Interface (ONFI) 1.0
Compliant
Multilevel cell (MLC) technology
Organization:
— Page size: 4,314 bytes (4,096 + 218 bytes)
— Block size: 128 pages (512K + 27K bytes)
— Plane size: 2,048 blocks
— Device size: 16Gb: 4,096 blocks; 32Gb:
8,192 blocks; 64Gb: 16,384 blocks
Read performance
— Random read: 50µs
— Sequential read: 20ns
Write performance
— Page program: 900µs (TYP)
— Block erase: 2ms (TYP)
Endurance:
— 5,000 PROGRAM/ERASE cycles
— Data Retention: JEDEC compliant
Operating Temperature
— Commercial: 0 to +70 °C
— Extended: -40 to +85 °C
Core Voltage (VCC): 2.7V - 3.6V
First block (block address 00h) guaranteed to
be valid when shipped from factory
Industry-standard basic NAND Flash command
set
Advanced command set:
— PROGRAM PAGE CACHE MODE
— PAGE READ CACHE MODE
— One-time programmable (OTP) commands
— Two-plane commands
— Interleaved die operations
— READ UNIQUE ID (contact factory)
— READ ID2 (contact factory)
Operation status byte provides a software
method of detecting:
— Operation completion
— Pass/fail condition
— Write-protect status
Ready/busy# (R/B#) signal provides a
hardware method of detecting PROGRAM or
ERASE cycle completion
WP# signal: Entire device hardware write
protect
Staggered Power-up Sequence: Issue RESET
command (FFH)
INTERNAL DATA MOVE operations supported
within the plane from which data is read
Package: 48 TSOP, Type I (Lead-Free Plating)
Intel Confidential
Document Number: 316339-001US
March 2007
Intel® MD516 NAND Flash Memory
7.8
7.9
7.10
7.7.2 TWO-PLANE PAGE READ 00h-00h-30h .......................................................44
7.7.3 TWO-PLANE RANDOM DATA READ 06h-E0h ................................................44
7.7.4 TWO-PLANE PROGRAM PAGE 80h-11h-81h-10h ..........................................46
7.7.5 TWO-PLANE PROGRAM PAGE CACHE MODE 80h-11h-80h-15h ......................47
7.7.6 TWO-PLANE INTERNAL DATA MOVE 00h-00h-35h/85h-11h-85h-10h .............49
7.7.7 TWO-PLANE READ for INTERNAL DATA MOVE 00h-00h-35h ..........................49
7.7.8 TWO-PLANE PROGRAM for INTERNAL DATA MOVE 85h-11h-85h-10h .............50
7.7.9 TWO-PLANE BLOCK ERASE 60h-D1h-60h-D0h ............................................53
Interleaved Die Operations..................................................................................54
7.8.1 TWO-PLANE/MULTIPLE-DIE READ STATUS 78h ...........................................54
7.8.2 Interleaved PROGRAM PAGE Operations.....................................................55
7.8.3 Interleaved PROGRAM PAGE CACHE MODE Operations .................................56
7.8.4 Interleaved TWO-PLANE PROGRAM PAGE Operation ....................................57
7.8.5 Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE Operations ...............58
7.8.6 Interleaved BLOCK ERASE Operations........................................................60
7.8.7 Interleaved TWO-PLANE BLOCK ERASE Operations ......................................61
RESET Operation ...............................................................................................63
7.9.1 RESET FFh .............................................................................................63
WRITE PROTECT Operation .................................................................................64
8.0 Error Management ...................................................................................................68
9.0 Timing Diagrams ......................................................................................................69
A Order Information....................................................................................................80
Intel® MD516 NAND Flash Memory
Advance Information DS
4
Intel Confidential
March 2007
Document Number: 316339-001US
4페이지 Intel® MD516 NAND Flash Memory
2.0
2.1
Functional Overview
This section provides an overview of the device in the following sections:
• Section 2.1, “Architecture”
• Section 2.2, “Memory Map and Addressing”
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
This provides a memory device with a low pin count. The commands received at the
I/O control circuits are latched by a command register and are transferred to control
logic circuits for generating internal signals to control device operations. The addresses
are latched by an address register and sent to a row decoder or a column decoder to
select a row address or a column address, respectively.
The data are transferred to or from the NAND Flash memory array, byte by byte,
through a data register and a cache register. The cache register is closest to I/O control
circuits and acts as a data buffer for the I/O data, whereas the data register is closest
to the memory array and acts as a data buffer for the NAND Flash memory array
operation.
The NAND Flash memory array is programmed and read in page-based operations and
is erased in block-based operations. During normal page operations, the data and
cache registers are tied together and act as a single register. During cache operations,
the data and cache registers operate independently to increase data throughput.
These devices also have a status register that reports the status of device operation.
NAND Flash devices do not contain dedicated address pins. Addresses are loaded using
a five-cycle sequence as shown in Section 2.2, “Memory Map and Addressing” on
page 8.
March 2007
Document Number: 316339-001US
Intel Confidential
Intel® MD516 NAND Flash Memory
DS
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