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W632GU8KB 데이터시트, 핀배열, 회로
W632GU8KB
32M 8 BANKS 8 BIT DDR3L SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................5
2. FEATURES ...........................................................................................................................................5
3. ORDER INFORMATION .......................................................................................................................6
4. KEY PARAMETERS .............................................................................................................................7
5. BALL CONFIGURATION ......................................................................................................................8
6. BALL DESCRIPTION............................................................................................................................9
7. BLOCK DIAGRAM ..............................................................................................................................11
8. FUNCTIONAL DESCRIPTION............................................................................................................12
8.1 Basic Functionality ..............................................................................................................................12
8.2 RESET and Initialization Procedure ....................................................................................................12
8.2.1
Power-up Initialization Sequence .....................................................................................12
8.2.2
Reset Initialization with Stable Power ..............................................................................14
8.3 Programming the Mode Registers.......................................................................................................15
8.3.1
Mode Register MR0 .........................................................................................................17
8.3.1.1
Burst Length, Type and Order ................................................................................17
8.3.1.2
CAS Latency...........................................................................................................18
8.3.1.3
Test Mode...............................................................................................................18
8.3.1.4
DLL Reset...............................................................................................................18
8.3.1.5
Write Recovery .......................................................................................................19
8.3.1.6
Precharge PD DLL .................................................................................................19
8.3.2
Mode Register MR1 .........................................................................................................19
8.3.2.1
DLL Enable/Disable................................................................................................20
8.3.2.2
Output Driver Impedance Control ...........................................................................20
8.3.2.3
ODT RTT Values ....................................................................................................20
8.3.2.4
Additive Latency (AL) .............................................................................................20
8.3.2.5
Write leveling ..........................................................................................................20
8.3.2.6
Output Disable........................................................................................................21
8.3.2.7
TDQS, TDQS#........................................................................................................21
8.3.3
Mode Register MR2 .........................................................................................................22
8.3.3.1
Partial Array Self Refresh (PASR) ..........................................................................23
8.3.3.2
CAS Write Latency (CWL) ......................................................................................23
8.3.3.3
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) .............................23
8.3.3.4
Dynamic ODT (Rtt_WR) .........................................................................................23
8.3.4
Mode Register MR3 .........................................................................................................24
8.3.4.1
Multi Purpose Register (MPR) ................................................................................24
8.4 No OPeration (NOP) Command..........................................................................................................25
8.5 Deselect Command.............................................................................................................................25
8.6 DLL-off Mode ......................................................................................................................................25
8.7 DLL on/off switching procedure...........................................................................................................26
8.7.1
DLL onto DLL offProcedure ..........................................................................26
8.7.2
DLL offto DLL onProcedure ..........................................................................27
8.8 Input clock frequency change..............................................................................................................28
8.8.1
Frequency change during Self-Refresh............................................................................28
8.8.2
Frequency change during Precharge Power-down ..........................................................28
Publication Release Date: Jan. 20, 2015
Revision: A05
-1-




W632GU8KB pdf, 반도체, 판매, 대치품
W632GU8KB
10.15.2
10.15.3
10.15.4
DDR3L-1600 Speed Bin and Operating Conditions .......................................................134
DDR3L-1866 Speed Bin and Operating Conditions .......................................................135
Speed Bin General Notes ..............................................................................................136
10.16
AC Characteristics ...................................................................................................................137
10.16.1
AC Timing and Operating Condition for -11 speed grade ..............................................137
10.16.2
AC Timing and Operating Condition for -12/12I/-15/15I speed grades...........................141
10.16.3
10.16.4
10.16.5
Timing Parameter Notes ................................................................................................145
Address / Command Setup, Hold and Derating .............................................................148
Data Setup, Hold and Slew Rate Derating .....................................................................155
11.
11.1
11.2
11.3
11.4
Backward Compatible to 1.5V DDR3 SDRAM VDD/VDDQ Requirements .......................................157
Input/Output Functional.....................................................................................................................157
Recommended DC Operating Conditions - DDR3L (1.35V) operation..............................................157
Recommended DC Operating Conditions - DDR3 (1.5V) operation..................................................157
VDDQ/VDDQ Voltage Switch between DDR3L and DDR3 ...............................................................157
12. PACKAGE SPECIFICATION ............................................................................................................159
13. REVISION HISTORY ........................................................................................................................160
Publication Release Date: Jan. 20, 2015
Revision: A05
-4-

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W632GU8KB 전자부품, 판매, 대치품
W632GU8KB
4. KEY PARAMETERS
Speed Bin
DDR3L-1866 DDR3L-1600 DDR3L-1333
CL-nRCD-nRP
Part Number Extension
13-13-13
-11
11-11-11
-12/12I
9-9-9
-15/15I
Unit
Parameter
Sym. Min. Max. Min. Max. Min. Max.
Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL
Internal read command to first data
fCKMAX
tAA
ACT to internal read or write delay time
tRCD
PRE command period
tRP
ACT to ACT or REF command period
ACT to PRE command period
tRC
tRAS
13.91
13.91
13.91
47.91
34
933 800 667 MHz
13.75
13.5
20 (13.125) *5 20 (13.125) *5 20
13.75
13.5
(13.125) *5 (13.125) *5
13.75
13.5
(13.125) *5 (13.125) *5
48.75
49.5
(48.125) *5 (49.125) *5
9 * tREFI 35 9 * tREFI 36 9 * tREFI
nS
nS
nS
nS
nS
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CWL = 5
CWL = 6
CWL = 6
CWL = 7
CWL = 7
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
2.5 3.3
Reserved
1.875
< 2.5
Reserved
1.5 < 1.875
2.5
1.875
1.875
1.5
1.5
3.3
< 2.5
< 2.5
< 1.875
< 1.875
2.5
1.875
1.875
1.5
1.5
3.3
< 2.5
< 2.5
< 1.875
< 1.875
nS
nS
nS
nS
nS
CL = 11
CWL = 8
CL = 13
CWL = 9
Supported CL Settings
Supported CWL Settings
Average periodic
refresh Interval
-40°C TCASE 85°C
0°C TCASE 85°C
85°C < TCASE 95°C
Operating One Bank Active-Precharge Current
Operating One Bank Active-Read-Precharge
Current
Operating Burst Read Current
Operating Burst Write Current
Burst Refresh Current
Self-Refresh Current, TOPER = 0 ~ 85°C
Operating Bank Interleave Current
tCK(AVG)
tCK(AVG)
Sup_CL
Sup_CWL
tREFI
IDD0
IDD1
IDD4R
IDD4W
IDD5B
IDD6
IDD7
Reserved
1.25
< 1.5
1.07 < 1.25
Reserved
6, 8, 10, 13
6, (7), 8, (9), 10, 11
5, 6, 7, 9
  *2
7.8 *1
3.9 *4
105
5, 6, 7, 8
7.8 *2, 3
7.8 *1
3.9 *4
95
120 115
250 220
230 200
145 140
19 19
360 340
Reserved
nS
Reserved
nS
6, (7), 8, 9, 10
nCK
5, 6, 7
7.8 *2, 3
7.8 *1
3.9 *4
nCK
μS
μS
μS
90 mA
110 mA
205 mA
180 mA
135 mA
19 mA
330 mA
Notes: (Field value contents in blue font or parentheses are optional AC parameter and CL setting)
1. All speed grades support 0°C TCASE 85°C with full JEDEC AC and DC specifications.
2. For -11, -12 and -15 speed grades, -40°C TCASE < 0°C is not available.
3. 12I and 15I speed grades support -40°C TCASE 85°C with full JEDEC AC and DC specifications.
4. For all speed grade parts, TCASE is able to extend to 95°C with doubling Auto Refresh commands in frequency to a 32 mS
period ( tREFI = 3.9 µS), it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range
capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1b, MR2 A7 is don't care).
5. For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 nS or lower. SPD settings must
be programmed to match. For example, DDR3L-1333 (9-9-9) devices supporting down binning to DDR3L-1066 (7-7-7) should
program 13.125 nS in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3L-1600 (11-11-11) devices
supporting down binning to DDR3L-1333 (9-9-9) or DDR3L-1066 (7-7-7) should program 13.125 nS in SPD bytes for tAAmin
(Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125 nS, tRCmin (Byte 21, 23) also
should be programmed accodingly. For example, 49.125nS (tRASmin + tRPmin = 36 nS + 13.125 nS) for DDR3L-1333 (9-9-9) and
48.125 nS (tRASmin + tRPmin = 35 nS + 13.125 nS) for DDR3L-1600 (11-11-11).
Publication Release Date: Jan. 20, 2015
Revision: A05
-7-

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