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W9725G8KB 데이터시트 PDF




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부품번호 W9725G8KB 기능
기능 8M x 4-BANKS x 8-BIT DDR2 SDRAM
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W9725G8KB 데이터시트, 핀배열, 회로
W9725G8KB
8M 4 BANKS 8 BIT DDR2 SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................4
2. FEATURES ...........................................................................................................................................4
3. ORDER INFORMATION .......................................................................................................................5
4. KEY PARAMETERS .............................................................................................................................5
5. BALL CONFIGURATION ......................................................................................................................6
6. BALL DESCRIPTION............................................................................................................................7
7. BLOCK DIAGRAM ................................................................................................................................8
8. FUNCTIONAL DESCRIPTION..............................................................................................................9
8.1 Power-up and Initialization Sequence ...................................................................................................9
8.2 Mode Register and Extended Mode Registers Operation ...................................................................10
8.2.1
Mode Register Set Command (MRS)...............................................................................10
8.2.2
Extend Mode Register Set Commands (EMRS) ..............................................................11
8.2.2.1
Extend Mode Register Set Command (1), EMR (1)................................................11
8.2.2.2
DLL Enable/Disable................................................................................................12
8.2.2.3
Extend Mode Register Set Command (2), EMR (2)................................................13
8.2.2.4
Extend Mode Register Set Command (3), EMR (3)................................................14
8.2.3
Off-Chip Driver (OCD) Impedance Adjustment ................................................................15
8.2.3.1
Extended Mode Register for OCD Impedance Adjustment ....................................16
8.2.3.2
OCD Impedance Adjust ..........................................................................................16
8.2.3.3
Drive Mode .............................................................................................................17
8.2.4
On-Die Termination (ODT)...............................................................................................18
8.2.5
ODT related timings .........................................................................................................18
8.2.5.1
MRS command to ODT update delay.....................................................................18
8.3 Command Function.............................................................................................................................20
8.3.1
Bank Activate Command..................................................................................................20
8.3.2
Read Command ...............................................................................................................20
8.3.3
Write Command ...............................................................................................................21
8.3.4
Burst Read with Auto-precharge Command.....................................................................21
8.3.5
Burst Write with Auto-precharge Command.....................................................................21
8.3.6
Precharge All Command ..................................................................................................21
8.3.7
Self Refresh Entry Command ..........................................................................................21
8.3.8
Self Refresh Exit Command .............................................................................................22
8.3.9
Refresh Command ...........................................................................................................22
8.3.10
No-Operation Command ..................................................................................................23
8.3.11
Device Deselect Command..............................................................................................23
8.4 Read and Write access modes ...........................................................................................................23
8.4.1
Posted CAS ....................................................................................................................23
Publication Release Date: Mar. 04, 2014
- 1 - Revision: A02




W9725G8KB pdf, 반도체, 판매, 대치품
W9725G8KB
1. GENERAL DESCRIPTION
The W9725G8KB is a 256M bits DDR2 SDRAM, organized as 8,388,608 words 4 banks 8 bits.
This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for general
applications. W9725G8KB is sorted into the following speed grades: -18, -25, 25A, 25K and -3.
The -18 grade parts is compliant to the DDR2-1066 (7-7-7) specification. The -25, 25A and 25K grade
parts are compliant to the DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification. The -3 grade parts is
compliant to the DDR2-667 (5-5-5) specification.
The automotive grade parts temperature, if offered, has two simultaneous requirements: ambient
temperature (TA) surrounding the device cannot be less than -40°C or greater than +95°C (for 25A),
+105°C (for 25K), and the case temperature (TCASE) cannot be less than -40°C or greater than +95°C
(for 25A), +105°C (for 25K). JEDEC specifications require the refresh rate to double when TCASE
exceeds +85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT
resistance and the input/output impedance must be derated when TCASE is < 0°C or > +85°C.
All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All
I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source
synchronous fashion.
2. FEATURES
Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK )
Data masks (DM) for write data.
Commands entered on each positive CLK edge, data and data mask are referenced to both edges
of DQS
Posted CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal
quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 60 Ball (8 x 12.5 mm2), using Lead free materials with RoHS compliant
Publication Release Date: Mar. 04, 2014
- 4 - Revision: A02

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W9725G8KB 전자부품, 판매, 대치품
W9725G8KB
6. BALL DESCRIPTION
BALL NUMBER SYMBOL
H8,H3,H7,J2,J8,J3,
J7,K2,K8,K3,H2,K7,
L2
A0A12
G2,G3
BA0BA1
C8,C2,D7,D3,D1,D9,
B1,B9
DQ0DQ7
F9 ODT
B7,A8
DQS, DQS
FUNCTION
DESCRIPTION
Address
Bank Select
Provide the row address for active commands, and the column
address and Auto-precharge bit for Read/Write commands to select
one location out of the memory array in the respective bank.
Row address: A0−A12.
Column address: A0−A9. (A10 is used for Auto-precharge)
BA0BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. Bank address also determines if the
mode register or one of the extended mode registers is to be
accessed during a MRS or EMRS command cycle.
Data Input
/ Output
Bi-directional data bus.
On Die Termination ODT (registered HIGH) enables termination resistance internal to the
Control
DDR2 SDRAM.
Data Strobe /
Differential Read
Data Strobe
Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write
data. DQS is only used when differential data strobe mode is
enabled via the control bit at EMR (1) [A10] = 0.
All commands are masked when CS is registered
G8
CS
Chip Select
HIGH. CS provides for external Rank selection on systems with
multiple Ranks. CS is considered part of the command code.
F7,G7,F3
B3
A2
RAS , CAS , Command Inputs RAS , CAS and WE (along with CS ) define the command being
WE entered.
DM/RDQS
Input Data Mask/
Read Data Strobe
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH coincident with that input data during a Write
access. DM is sampled on both edges of DQS. Although DM is input
only, the DM loading matches the DQ and DQS loading. When
RDQS is enabled, RDQS is output with read data only and is ignored
during write data. RDQS is enabled by EMR (1) [A11] = 1. If RDQS is
enabled, the DM function is disabled.
NU/ RDQS
Not Use/Differential
Read Data Strobe
RDQS is only used when RDQS is enabled and differential data
strobe mode is enabled. If differential data strobe mode is disabled
via the control bit at EMR (1) [A10] = 1, then ball A2 and A8 are not
used.
E8,F8
F2
E2
A1,E9,H9,L1
A3,E3,J1,K9
A9,C1,C3,C7,C9
A7,B2,B8,D2,D8
G1,L3,L7,L8
E1
E7
CLK, CLK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
VDDL
VSSDL
Differential Clock
Inputs
Clock Enable
Reference Voltage
Power Supply
Ground
DQ Power Supply
DQ Ground
No Connection
DLL Power Supply
DLL Ground
CLK and CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK
and negative edge of CLK . Output (read) data is referenced to the
crossings of CLK and CLK (both directions of crossing).
CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM.
VREF is reference voltage for inputs.
Power Supply: 1.8V ± 0.1V.
Ground.
DQ Power Supply: 1.8V ± 0.1V.
DQ Ground. Isolated on the device for improved noise immunity.
No connection.
DLL Power Supply: 1.8V ± 0.1V.
DLL Ground.
Publication Release Date: Mar. 04, 2014
- 7 - Revision: A02

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W9725G8KB

8M x 4-BANKS x 8-BIT DDR2 SDRAM

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