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PDF TSM1285 Data sheet ( Hoja de datos )
| Número de pieza | TSM1285 | |
| Descripción | Low-Power 12-Bit Serial-output ADC | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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TSM1285
A 300ksps, Single-supply, Low-Power 12-Bit Serial-output ADC
FEATURES
Alternate Source for MAX1285 and higher-speed
upgrade to MAX1240 and MAX1241
Single-Supply Operation: +2.7V to +3.6V
DNL & INL: ±1LSB (max)
300ksps Sampling Rate
Low Conversion-Mode Supply Current:
2.5mA @ 300ksps
Low Supply Current in Shutdown: 2µA
Internal Track-and-Hold
Internal +2.5V Reference
SPI®/QSPI™/MICROWIRE™ 3-Wire Serial-
Interface1
8-Pin SOIC Package
APPLICATIONS
Process Control and Factory Automation
Data and Low-frequency Signal Acquisition
Portable Data Logging
Pen Digitizers & Tablet Computers
Medical Instrumentation
Battery-powered Instruments
DESCRIPTION
The TSM1285 – a single-supply, single-channel, 12-
bit analog-to-digital converter (ADC) - is an alternate
source for the MAX1285 and a higher-speed upgrade
to the MAX1240 and MAX1240 ADCs. The TSM1285
combines a high-bandwidth track-and-hold (T/H), a
high-speed serial digital interface, an internal +2.5V
reference, and low conversion-mode power
consumption. The TSM1285 operates from a single
+2.7V to+3.6V supply and draws less than 2.5mA at
300ksps.
Connecting directly to any SPI, QSPI, MICROWIRE™
microcontrollers and other interface-compatible
computing devices, the TSM1285’s 3-wire serial
interface is easy to use and doesn’t require separate,
external logic. An external serial-interface clock
controls the TSM1285’s conversion process and its
output shift register operation.
In PCB-space-conscious, low-power remote-sensor
and data-acquisition applications, the TSM1285 is an
excellent choice for its low-power, ease-of-use, and
small-package-footprint attributes.
1 SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National
Semiconductor Corporation.
The TSM1285BC is fully specified over the
0°C to +70°C temperature range. TSM1285BE is fully
specified over the -40°C to +85°C temperature range.
Both products are available in a 8-pin SOIC package.
FUNCTIONAL BLOCK DIAGRAM
Page 1
© 2014 Silicon Laboratories, Inc. All rights reserved.
1 page  
TSM1285
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = +3V; fSCLK = 4.8MHz; CLOAD = 20pF; 4.7μF capacitor at REF; TA = 25ºC, unless otherwise noted.
Integral Nonlinearity
0.4
0.3
0.2
0.1
0
0.25
0.2
0.15
0.2
0.05
0
Differential Nonlinearity
-0.1
-0.2
-0.3
-0.4
0
1k 2k 3k 4k 5k
-0.05
-0.1
-0.15
-0.2
-0.25
0
1k 2k 3k 4k 5k
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
Offset Error vs Supply Voltage
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
2.7 2.88 3.06 3.24 3.42 3.6
POWER SUPPLY VOLTAGE - Volt
Offset Error vs Temperature
1
0.5
0
-0.5
-1
-1.5
-2
-40
-15 10 35 60
TEMPERATURE - ºC
85
Gain Error vs Supply Voltage
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
2.7 2.88 3.06 3.24 3.42 3.6
POWER SUPPLY VOLTAGE - Volt
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-40
Gain Error vs Temperature
-15 10 35 60
TEMPERATURE - ºC
85
TSM1285 Rev. 1.0
Page 5
5 Page 
Figure 7: TSM1285 Reference Power-Up Delay
vs Duration in Shutdown Mode
2.5
CREF = 4.7µF
2
1.5
1
0.5
0
0.1m 1m
10m 100m
1
10
TIME IN SHUTDOWN MODE - sec
TSM1285
APPLICATIONS INFORMATION
Connection to Industry-Standard Serial Interfaces
The TSM1285’s serial interface is fully compatible
with SPI/QSPI and MICROWIRE standard serial
interfaces (Refer to Figure 11). For serial interface
operation with these standards, the CPU’s serial
interface should be set to master mode so the CPU
then generates the serial clock. Second, the CPU’s
serial clock should be configured to operate up to
4.8MHz. The process to configure the serial clock and
data transfer operation is as follows:
1) Using a general-purpose I/O line from the CPU, the
CS pin is driven low to start a conversion. DOUT
transitions from high impedance to logic low. The
SCLK polarity should be low to start the conversion
process correctly.
Figure 8: TSM1285 Serial Interface Timing Sequence
Figure 9: TSM1285 Serial Interface Timing Specifications in Detail.
2) Next, SCLK is activated for a minimum of 15 SCLK
cycles where the first two SCLKs produce zeros at
the DOUT pin. Data at DOUT is formatted MSB first
and DOUT transitions occur 20ns after the third (3rd)
SCLK low-to-high transition. Once the low-to-high
SCLK transition has occurred, data is valid at DOUT
TSM1285 Rev. 1.0
Page 11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet TSM1285.PDF ] | |
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