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PDF COP688EB Data sheet ( Hoja de datos )
| Número de pieza | COP688EB | |
| Descripción | 8-Bit CMOS ROM Based Microcontrollers with 8k Memory/ CAN Interface/ 8-Bit A/D/ and USART | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de COP688EB (archivo pdf) en la parte inferior de esta página. Total 34 Páginas | ||
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PRELIMINARY
September 1996
COP87L88CL COP87L84CL 8-Bit
One-Time Programmable (OTP) Microcontroller
General Description
The COP87L88CL COP87L84CL OTP microcontrollers are
members of the COP8TM feature family using an 8-bit core
architecture It is pin and software compatible to the mask
ROM COP888CL COP884CL product family
(Continued)
Key Features
Y Two 16-bit timers each with two
supporting
Processor independent PWM mode
External event counter mode
Input capture mode
16-bit
registers
Y 4 kbytes on-board EPROM with security feature
Y 128 bytes on-board RAM
Additional Peripheral Features
Y Idle timer
Y Multi-Input Wake-Up (MIWU) with optional interrupts (8)
Y WATCHDOGTM and clock monitor logic
Y MICROWIRE PLUSTM serial I O
I O Features
Y Memory mapped I O
Y Software selectable I O options (TRI-STATE output
push-pull output weak pull-up input high impedance in-
put)
Y Schmitt trigger inputs on ports G and L
Y Packages
44 PLCC with 39 I O pins
40 DIP with 33 I O pins
28 DIP with 24 I O pins
28 SO with 24 I O pins (contact local sales office for
availability)
CPU Instruction Set Features
Y 1 ms instruction cycle time
Y Ten multi-source vectored interrupts servicing
External interrupt
Idle timer T0
Two timers (each with 2 Interrupts)
MICROWIRE PLUS
Multi-Input Wake Up
Software trap
Default VIS (default interrupt)
Y Versatile and easy to use instruction set
Y 8-bit Stack Pointer SP stack in RAM
Y Two 8-bit register indirect data memory pointers
(B and X)
Fully Static CMOS
Y Two power saving modes HALT and IDLE
Y Single supply operation 2 7V – 5 5V
Y Temperature range b40 C to a85 C
Development Support
Y Emulation device for the COP888CL COP884CL
Y Real time emulation and full program debug offered by
MetaLink Development System
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRE PLUSTM WATCHDOGTM MICROWIRETM and COP8TM are trademarks of National Semiconductor Corporation
PC is a registered trademark of International Business Machines Corporation
iceMASTERTM is a trademark of MetaLink Corporation
C1996 National Semiconductor Corporation TL DD12524
RRD-B30M106 Printed in U S A
TL DD 12524 – 16
http www national com
1 page  
AC Electrical Characteristics b40 C s TA s a85 C unless otherwise specified
Parameter
Conditions
Min Typ Max Units
Instruction Cycle Time (tc)
Crystal or Resonator
R C Oscillator
1 DC ms
3 DC
Inputs
tSETUP
tHOLD
Output Propagation Delay
tPD1 tPD0
SO SK
All Others
MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tUPD)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
RL e 2 2k CL e 100 pF
4V s VCC s 6V
4V s VCC s 6V
200
60
20
56
1
1
1
1
ns
ms
07
1
ns
220
tc
Reset Pulse Width
1 ms
TL DD 12524 – 4
FIGURE 2 MICROWIRE PLUS Timing
5 http www national com
5 Page 
Timers (Continued)
FIGURE 7 Timer in External Event Counter Mode
TL DD 12524 – 10
Mode 3 Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block Tx in the
input capture mode
In this mode the timer Tx is constantly running at the fixed
tc rate The two registers RxA and RxB act as capture
registers Each register acts in conjunction with a pin The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin Control bits
TxC3 TxC2 and TxC1 allow the trigger events to be speci-
fied either as a positive or a negative edge The trigger con-
dition for each input pin can be specified independently
The trigger conditions can also be programmed to generate
interrupts The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags TxPNDA and TxPNDB The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin Similarly the flag TxENB controls the interrupts
from the TxB pin
Underflows from the timer can also be programmed to gen-
erate interrupts Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under-
flow interrupt pending flag in the Input Capture mode) Con-
sequently the TxC0 control bit should be reset when enter-
ing the Input Capture mode The timer underflow interrupt is
enabled with the TxENA control flag When a TxA interrupt
occurs in the Input Capture mode the user must check both
whether a TxA input capture or a timer underflow (or both)
caused the interrupt
Figure 8 shows a block diagram of the timer in Input Capture
mode
TIMER CONTROL FLAGS
The timers T1 and T2 have indentical control structures
The control bits and their functions are summarized below
TxC0
Timer Start Stop control in Modes 1 and 2
(Processor Independent PWM and External
Event Counter) where 1 e Start 0 e Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
TxENA
TxENB
Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1 e Timer Interrupt Enabled
0 e Timer Interrupt Disabled
TxC3
TxC2
TxC1
Timer mode control
Timer mode control
Timer mode control
FIGURE 8 Timer in Input Capture Mode
11
TL DD 12524 – 11
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| Páginas | Total 34 Páginas | |
| PDF Descargar | [ Datasheet COP688EB.PDF ] | |
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