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PDF COP688GD Data sheet ( Hoja de datos )
| Número de pieza | COP688GD | |
| Descripción | 8-Bit CMOS ROM Based Microcontrollers with 16k | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
August 1996
COP87L88GG
8-Bit One-Time Programmable (OTP) Microcontroller
with UART and Three Multi-Function Timers
General Description
The COP87L88GG OTP microcontroller is a member of the
COP8TM feature family using an 8-bit core architecture It is
pin and software compatible to the mask ROM COP888GG
product family
(Continued)
Features
Y Full duplex UART
Y Three 16-bit timers each with two 16-bit registers
supporting
Processor independent PWM mode
External event counter mode
Input capture mode
Y 16 kbytes on-board OTP EPROM with security feature
Y 512 bytes on-board RAM
Additional Peripheral Features
Y Idle Timer
Y Multi-Input Wakeup (MIWU) with optional interrupts (8)
Y WATCHDOGTM and clock monitor logic
Y Two analog comparators
Y MICROWIRE PLUSTM serial I O
I O Features
Y Memory mapped I O
Y Software selectable I O options (TRI-STATE output
push-pull output weak pull-up input high impedance in-
put)
Y Schmitt trigger inputs on ports G and L
Y Packages
40 DIP with 36 I O pins
44 PLCC with 40 I O pins
CPU Instruction Set Features
Y 1 ms instruction cycle time
Y Fourteen multi-source vectored interrupts servicing
External interrupt with selectable edge
Idle Timer T0
Three Timers (each with 2 interrupts)
MICROWIRE PLUS
Multi-Input Wakeup
Software trap
UART (2)
Default VIS (default interrupt)
Y Versatile and easy to use instruction set
Y 8-bit Stack Pointer SP (stack in RAM)
Y Two 8-bit register indirect data memory pointers
(B and X)
Fully Static CMOS
Y Two power saving modes HALT and IDLE
Y Single supply operation 2 7V – 5 5V
Y Temperature ranges b40 C to a85 C
Development Support
Y Emulation device for the COP888GG and COP888HG
Y Real time emulation and full program debug offered by
MetaLink Development System
Block Diagram
FIGURE 1 Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRE PLUSTM COP8TM and WATCHDOGTM are trademarks of National Semiconductor Corporation
PC is a registered trademark of International Business Machines Corporation
iceMASTERTM is a trademark of MetaLink Corporation
C1996 National Semiconductor Corporation TL DD12532
RRD-B30M96 Printed in U S A
TL DD 12532 – 1
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1 page  
AC Electrical Characteristics b40 C s TA s a85 C unless otherwise specified
Parameter
Conditions
Min Typ Max Units
Instruction Cycle Time (tc)
Crystal Resonator
R C Oscillator
Inputs
tSETUP
tHOLD
Output Propagation Delay (Note 6)
tPD1 tPD0
SO SK
All Others
MICROWIRE Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tUPD)
Input Pulse Width (Note 7)
Interrupt Input High Time
Interrupt Input Low Time
Timer 1 2 3 Input High Time
Timer 1 2 3 Input Low Time
Reset Pulse Width
2 7V s VCC s 4 5V
4 5V s VCC s 5 5V
2 7V s VCC s 4 5V
4 5V s VCC s 5 5V
4 5V s VCC s 5 5V
2 7V s VCC s 4 5V
4 5V s VCC s 5 5V
2 7V s VCC s 4 5V
RL e 2 2k CL e 100 pF
4 5V s VCC s 5 5V
2 7V s VCC s 4 5V
4 5V s VCC s 5 5V
2 7V s VCC s 4 5V
VCC t 4 5V
VCC t 4 5V
VCC t 4 5V
25
1
75
3
200
500
60
150
20
56
10
10
10
10
10
DC ms
DC ms
DC ms
DC ms
ns
ns
ns
ns
07
1 75
10
25
220
ms
ms
ms
ms
ns
ns
ns
tc
tc
tc
tc
ms
tc e Instruction Cycle Time
Note 1 Maximum rate of voltage change must be k 0 5 V ms
Note 2 Supply and IDLE currents are measured with CKI driven with a square wave Oscillator CKO driven 180 out of phase with CKI inputs connected to VCC
and outputs driven low but not connected to a load
Note 3 The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high Test Conditions All inputs tied to VCC L and G
ports in the TRI-STATE mode and tied to ground all outputs low and tied to ground The clock monitor is disabled
Note 4 The user must guarantee that D2 pin does not source more than 10 mA during RESET If D2 sources more than 10 mA during reset the device will go into
programming mode
Note 5 Pins G6 and RESET are designed with a high voltage input network These pins allow input voltages l VCC and the pins will have sink current to VCC when
biased at voltages l VCC (the pins do not have source current when biased at a voltage below VCC) The effective resistance to VCC is 750X (typical) These two
pins will not latch up The voltage at the pins must be limited to k 14V WARNING Voltages in excess of 14V will cause damage to the pins This warning
excludes ESD transients
Note 6 The output propagation delay is referenced to the end of the instruction cycle where the output change occurs
Note 7 Parameter characterized but not tested
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5 Page 
Control Registers
CNTRL Register (Address X 00EE)
The Timer1 (T1) and MICROWIRE PLUS control register
contains the following bits
SL1 SL0 Select the MICROWIRE PLUS clock divide
by (00 e 2 01 e 4 1x e 8)
IEDG
External interrupt edge polarity select
(0 e Rising edge 1 e Falling edge)
MSEL
Selects G5 and G4 as MICROWIRE PLUS
signals SK and SO respectively
T1C0
Timer T1 Start Stop control in timer
modes 1 and 2
Timer T1 Underflow Interrupt Pending Flag in
timer mode 3
T1C1
Timer T1 mode control bit
T1C2
Timer T1 mode control bit
T1C3
Timer T1 mode control bit
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
Bit 7
Bit 0
PSW Register (Address X 00EF)
The PSW register contains the following select bits
GIE Global interrupt enable (enables interrupts)
EXEN Enable external interrupt
BUSY MICROWIRE PLUS busy shifting flag
EXPND External interrupt pending
T1ENA Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1 T1 Underflow in Mode 2 T1A cap-
ture edge in mode 3)
C Carry Flag
HC Half Carry Flag
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7
Bit 0
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the car-
ry flags In addition to the SC and RC instructions ADC
SUBC RRC and RLC instructions affect the carry and Half
Carry flags
ICNTRL Register (Address X 00E8)
The ICNTRL register contains the following bits
T1ENB Timer T1 Interrupt Enable for T1B Input capture
edge
T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
mWEN Enable MICROWIRE PLUS interrupt
mWPND MICROWIRE PLUS interrupt pending
T0EN Timer T0 Interrupt Enable (Bit 12 toggle)
T0PND Timer T0 Interrupt pending
LPEN
L Port Interrupt Enable (Multi-Input Wakeup In-
terrupt)
Bit 7 could be used as a flag
Unused LPEN T0PND T0EN mWPND mWEN T1PNDB T1ENB
Bit 7
Bit 0
T2CNTRL Register (Address X 00C6)
The T2CNTRL register contains the following bits
T2ENB Timer T2 Interrupt Enable for T2B Input capture
edge
T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-
ture edge
T2ENA Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1 T2 Underflow in mode 2 T2A cap-
ture edge in mode 3)
T2C0
Timer T2 Start Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3
T2C1 Timer T2 mode control bit
T2C2 Timer T2 mode control bit
T2C3 Timer T2 mode control bit
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
Bit 7
Bit 0
T3CNTRL Register (Address X 00B6)
The T3CNTRL register contains the following bits
T3ENB Timer T3 Interrupt Enable for T3B Input capture
edge
T3PNDB Timer T3 Interrupt Pending Flag for T3B cap-
ture edge
T3ENA Timer T3 Interrupt Enable for Timer Underflow
or T3A Input capture edge
T3PNDA Timer T3 Interrupt Pending Flag (Autoload RA
in mode 1 T3 Underflow in mode 2 T3A cap-
ture edge in mode 3)
T3C0
Timer T3 Start Stop control in timer modes 1
and 2
Timer T3 Underflow Interrupt Pending Flag in
timer mode 3
T3C1 Timer T3 mode control bit
T3C2 Timer T3 mode control bit
T3C3 Timer T3 mode control bit
T3C3 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB
Bit 7
Bit 0
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet COP688GD.PDF ] | |
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