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PDF COP884CG Data sheet ( Hoja de datos )
| Número de pieza | COP884CG | |
| Descripción | 8-Bit CMOS ROM Based Microcontrollers with 4k to 24k Memory/ Comparators and USART | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 1996
COP884CG COP888CG 8-Bit Microcontroller
with UART and Three Multi-Function Timers
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconduc-
tor’s M2CMOSTM process technology The COP888CG is a
member of this expandable 8-bit core processor family of
microcontrollers
(Continued)
Key Features
Y Full duplex UART
Y Three 16-bit timers each with two 16-bit registers sup-
porting
Processor independent PWM mode
External event counter mode
Input capture mode
Y Quiet design (low radiated emissions)
Y 4 kbytes of on-chip ROM
Y 192 bytes of on-chip RAM
Additional Peripheral Features
Y Idle timer
Y Multi-Input Wake Up (MIWU) with optional interrupts (8)
Y Two analog comparators
Y WATCHDOGTM and Clock Monitor logic
Y MICROWIRE PLUSTM serial I O
I O Features
Y Memory mapped I O
Y Software selectable I O options (TRI-STATE output
push-pull output weak pull-up input high impedance in-
put)
Y High current outputs
Y Schmitt trigger inputs on Port G
Y Packages
44 PLCC with 40 I O pins
40 DIP with 36 I O pins
28 DIP with 24 I O pins
28 SO with 24 I O pins
CPU Instruction Set Feature
Y 1 ms instruction cycle time
Y Fourteen multi-source vectored interrupts servicing
External interrupt with selectable edge
Idle timer T0
Three timers (each with 2 interrupts)
MICROWIRE PLUS
Multi-Input WAke Up
Software trap
UART (2)
Default VIS (default interrupt)
Y Versatile and easy to use instruction set
Y 8-bit Stack Pointer (SP) stack in RAM
Y Two 8-bit register indirect data memory pointers (B X)
Fully Static CMOS
Y Low current drain (typically k 1 mA)
Y Single supply operation 2 5V to 6 0V
Y Temperature range b40 C to a85 C
Development Support
Y Emulation and OTP devices
Y Real time emulation and full program debug offered by
MetaLink Development System
Block Diagram
FIGURE 1 Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRE PLUSTM M2CMOSTM COP8TM microcontrollers MICROWIRETM and WATCHDOGTM are trademarks of National Semiconductor Corporation
iceMASTERTM is a trademark of MetaLink Corporation
C1996 National Semiconductor Corporation TL DD 9765
RRD-B30M106 Printed in U S A
TL DD 9765 – 1
http www national com
Free Datasheet http://www.datasheet4u.com/
1 page  
DC Electrical Characteristics b40 C s TA s a85 C unless otherwise specified (Continued)
Parameter
Conditions
Min Typ
Max
Allowable Sink Source
Current per Pin
D Outputs (Sink)
All others
15
3
Maximum Input Current
without Latchup
TA e 25 C
g100
RAM Retention Voltage Vr
500 ns Rise
and Fall Time (Min)
2
Input Capacitance
7
Load Capacitance on D2
1000
AC Electrical Characteristics b40 C s TA s a85 C unless otherwise specified
Parameter
Conditions
Min Typ
Instruction Cycle Time (tc)
Crystal Resonator
R C Oscillator
Inputs
tSETUP
tHOLD
Output Propagation Delay (Note 4)
tPD1 tPD0
SO SK
All Others
MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tUPD)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
4V s VCC s 6V
2 5V s VCC k 4V
4V s VCC s 6V
2 5V s VCC k 4V
4V s VCC s 6V
2 5V s VCC k 4V
4V s VCC s 6V
2 5V s VCC k 4V
RL e 2 2k CL e 100 pF
4V s VCC s 6V
2 5V s VCC k 4V
4V s VCC s 6V
2 5V s VCC k 4V
1
25
3
75
200
500
60
150
20
56
1
1
1
1
Reset Pulse Width
1
Note 4 The output propagation delay is referenced to the end of the instruction cycle where the output change occurs
Max
DC
DC
DC
DC
07
1 75
1
25
220
Units
mA
mA
mA
V
pF
pF
Units
ms
ms
ms
ms
ns
ns
ns
ns
ms
ms
ms
ms
ns
ns
ns
tc
tc
tc
tc
ms
5 http www national com
Free Datasheet http://www.datasheet4u.com/
5 Page 
Timers (Continued)
TIMER T1 TIMER T2 AND TIMER T3
The device has a set of three powerful timer counter
blocks T1 T2 and T3 The associated features and func-
tioning of a timer block are described by referring to the
timer block Tx Since the three timer blocks T1 T2 and T3
are identical all comments are equally applicable to any of
the three timer blocks
Each timer block consists of a 16-bit timer Tx and two
supporting 16-bit autoreload capture registers RxA and
RxB Each timer block has two pins associated with it TxA
and TxB The pin TxA supports I O required by the timer
block while the pin TxB is an input to the timer block The
powerful and flexible timer block allows the device to easily
perform all timer functions with minimal software overhead
The timer block has three operating modes Processor Inde-
pendent PWM mode External Event Counter mode and
Input Capture mode
The control bits TxC3 TxC2 and TxC1 allow selection of
the different modes of operation
Mode 1 Processor Independent PWM Mode
As the name suggests this mode allows the device to gen-
erate a PWM signal with very minimal user intervention The
user only has to define the parameters of the PWM signal
(ON time and OFF time) Once begun the timer block will
continuously generate the PWM signal completely indepen-
dent of the microcontroller The user software services the
timer block only when the PWM parameters require updat-
ing
In this mode the timer Tx counts down at a fixed rate of tc
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers RxA and RxB The very
first underflow of the timer causes the timer to reload from
the register RxA Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB
The Tx Timer control bits TxC3 TxC2 and TxC1 set up the
timer for PWM mode operation
Figure 7 shows a block diagram of the timer in PWM mode
The underflows can be programmed to toggle the TxA out-
put pin The underflows can also be programmed to gener-
ate interrupts
Underflows from the timer are alternately latched into two
pending flags TxPNDA and TxPNDB The user must reset
these pending flags under software control Two control en-
able flags TxENA and TxENB allow the interrupts from the
timer underflow to be enabled or disabled Setting the timer
enable flag TxENA will cause an interrupt when a timer un-
derflow causes the RxA register to be reloaded into the tim-
er Setting the timer enable flag TxENB will cause an inter-
rupt when a timer underflow causes the RxB register to be
reloaded into the timer Resetting the timer enable flags will
disable the associated interrupts
Either or both of the timer underflow interrupts may be en-
abled This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output Alternatively the user may choose to interrupt
on both edges of the PWM output
TL DD 9765 – 14
FIGURE 7 Timer in PWM Mode
Mode 2 External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above The main difference is that
the timer Tx is clocked by the input signal from the TxA pin
The Tx timer control bits TxC3 TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin Underflows from the timer are latched into
the TxPNDA pending flag Setting the TxENA control flag
will cause an interrupt when the timer underflows
In this mode the input pin TxB can be used as an indepen-
dent positive edge sensitive interrupt input if the TxENB
control flag is set The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag
Figure 8 shows a block diagram of the timer in External
Event Counter mode
Note The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock
TL DD 9765 – 15
FIGURE 8 Timer in External Event Counter Mode
Mode 3 Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block Tx in the
input capture mode
In this mode the timer Tx is constantly running at the fixed
tc rate The two registers RxA and RxB act as capture
registers Each register acts in conjunction with a pin The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin
11 http www national com
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 43 Páginas | |
| PDF Descargar | [ Datasheet COP884CG.PDF ] | |
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