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부품번호 COP8SBR9LVA8 기능
기능 8-Bit CMOS Flash Based Microcontroller with 32k Memory/ Virtual EEPROM and Brownout
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COP8SBR9LVA8 데이터시트, 핀배열, 회로
August 2003
COP8SBR9/COP8SCR9/COP8SDR9
8-Bit CMOS Flash Based Microcontroller with 32k
Memory, Virtual EEPROM and Brownout
1.0 General Description
The COP8SBR9/SCR9/SDR9 Flash based microcontrollers
are highly integrated COP8Feature core devices, with 32k
Flash memory and advanced features including Virtual EE-
PROM, High Speed Timers, USART, and Brownout Reset.
This single-chip CMOS device is suited for applications re-
quiring a full featured, in-system reprogrammable controller
with large memory and low EMI. The same device is used for
development, pre-production and volume production with a
range of COP8 software and hardware development tools.
Devices included in this datasheet:
Device
Flash Program
Memory
(bytes)
RAM
(bytes)
COP8SBR9
32k
1k
COP8SCR9
32k
1k
COP8SDR9
32k
1k
Brownout
Voltage
2.7V to 2.9V
4.17V to 4.5V
No Brownout
I/O
Pins
Packages
37,39,49,
59
37,39,49,
59
37,39,49,
59
44 LLP,
44/68 PLCC,
48/56 TSSOP
44 LLP,
44/68 PLCC,
48/56 TSSOP
44 LLP,
44/68 PLCC,
48/56 TSSOP
Temperature
−40˚C to +85˚C
−40˚C to +85˚C
−40˚C to +125˚C
−40˚C to +85˚C
−40˚C to +125˚C
2.0 Features
KEY FEATURES
n 32 kbytes Flash Program Memory with Security Feature
n Virtual EEPROM using Flash Program Memory
n 1 kbyte volatile RAM
n USART with on chip baud generator
n 2.7V–5.5V In-System Programmability of Flash
n High endurance - 100k Read/Write Cycles
n Superior data retention - 100 years
n Dual Clock Operation with HALT/IDLE Power Save
Modes
n Three 16-bit timers:
— Timers T2 and T3 can operate at high speed (50 ns
resolution)
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n Brown-out Reset (COP8SBR9/SCR9)
OTHER FEATURES
n Single supply operation: 2.7V–5.5V
n Quiet Design (low radiated emissions)
n Multi-Input Wake-up with optional interrupts
n MICROWIRE/PLUS (Serial Peripheral Interface
Compatible)
n Clock Doubler for 20 MHz operation from 10 MHz
Oscillator, with 0.5 µs Instruction Cycle
n Thirteen multi-source vectored interrupts servicing:
— External Interrupt
— USART (2)
— Idle Timer T0
— Three Timers (each with 2 interrupts)
— MICROWIRE/PLUS Serial peripheral interface
— Multi-Input Wake-Up
— Software Trap
n Idle Timer with programmable interrupt interval
n 8-bit Stack Pointer SP (stack in RAM)
n Two 8-bit Register Indirect Data Memory Pointers
n True bit manipulation
n WATCHDOG and Clock Monitor logic
n Software selectable I/O options
— TRI-STATE® Output/High Impedance Input
— Push-Pull Output
— Weak Pull Up Input
n Schmitt trigger inputs on I/O ports
n High Current I/Os
n Temperature range: –40˚C to +85˚C and –40˚C to
+125˚C (COP8SCR9/SDR9)
n Packaging: 44 and 68 PLCC, 44 LLP, 48 and 56 TSSOP
n True In-System, Real time emulation and debug offered
by MetaLink’s Development Systemstools available
COP8is a trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation DS101389
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COP8SBR9LVA8 pdf, 반도체, 판매, 대치품
Table of Contents (Continued)
12.1.1 ITMR Register .................................................................................................................................. 34
12.2 TIMER T1, TIMER T2, AND TIMER T3 ................................................................................................ 35
12.2.1 Timer Operating Speeds .................................................................................................................. 35
12.2.2 Mode 1. Processor Independent PWM Mode ................................................................................. 35
12.2.3 Mode 2. External Event Counter Mode ........................................................................................... 36
12.2.4 Mode 3. Input Capture Mode .......................................................................................................... 36
12.3 TIMER CONTROL FLAGS .................................................................................................................... 36
13.0 Power Saving Features ............................................................................................................................ 37
13.1 POWER SAVE MODE CONTROL REGISTER .................................................................................... 38
13.2 OSCILLATOR STABILIZATION ............................................................................................................. 39
13.3 HIGH SPEED MODE OPERATION ...................................................................................................... 39
13.3.1 High Speed Halt Mode .................................................................................................................... 39
13.3.1.1 Entering The High Speed Halt Mode ......................................................................................... 39
13.3.1.2 Exiting The High Speed Halt Mode ........................................................................................... 39
13.3.1.3 HALT Exit Using Reset .............................................................................................................. 39
13.3.1.4 HALT Exit Using Multi-Input Wake-up ....................................................................................... 39
13.3.1.5 Options ....................................................................................................................................... 39
13.3.2 High Speed Idle Mode ..................................................................................................................... 40
13.4 DUAL CLOCK MODE OPERATION ...................................................................................................... 40
13.4.1 Dual Clock HALT Mode ................................................................................................................... 41
13.4.1.1 Entering The Dual Clock Halt Mode .......................................................................................... 41
13.4.1.2 Exiting The Dual Clock Halt Mode ............................................................................................. 41
13.4.1.3 HALT Exit Using Reset .............................................................................................................. 41
13.4.1.4 HALT Exit Using Multi-Input Wake-up ....................................................................................... 41
13.4.1.5 Options ....................................................................................................................................... 41
13.4.2 Dual Clock Idle Mode ...................................................................................................................... 41
13.5 LOW SPEED MODE OPERATION ....................................................................................................... 42
13.5.1 Low Speed HALT Mode ................................................................................................................... 42
13.5.1.1 Entering The Low Speed Halt Mode ......................................................................................... 42
13.5.1.2 Exiting The Low Speed Halt Mode ............................................................................................ 42
13.5.1.3 HALT Exit Using Reset .............................................................................................................. 42
13.5.1.4 HALT Exit Using Multi-Input Wake-up ....................................................................................... 42
13.5.1.5 Options ....................................................................................................................................... 42
13.5.2 Low Speed Idle Mode ...................................................................................................................... 42
13.6 MULTI-INPUT WAKE-UP ...................................................................................................................... 43
14.0 USART ..................................................................................................................................................... 44
14.1 USART CONTROL AND STATUS REGISTERS ................................................................................... 45
14.2 DESCRIPTION OF USART REGISTER BITS ...................................................................................... 45
14.3 ASSOCIATED I/O PINS ........................................................................................................................ 46
14.4 USART OPERATION ............................................................................................................................ 46
14.4.1 Asynchronous Mode ........................................................................................................................ 47
14.4.2 Synchronous Mode .......................................................................................................................... 47
14.5 FRAMING FORMATS ............................................................................................................................ 47
14.6 USART INTERRUPTS .......................................................................................................................... 48
14.7 BAUD CLOCK GENERATION .............................................................................................................. 48
14.8 EFFECT OF HALT/IDLE ....................................................................................................................... 50
14.9 DIAGNOSTIC ........................................................................................................................................ 50
14.10 ATTENTION MODE ............................................................................................................................. 50
14.11 BREAK GENERATION ........................................................................................................................ 50
15.0 Interrupts .................................................................................................................................................. 51
15.1 INTRODUCTION ................................................................................................................................... 51
15.2 MASKABLE INTERRUPTS ................................................................................................................... 51
15.3 VIS INSTRUCTION ............................................................................................................................... 52
15.3.1 VIS Execution .................................................................................................................................. 53
15.4 NON-MASKABLE INTERRUPT ............................................................................................................ 54
15.4.1 Pending Flag .................................................................................................................................... 54
15.4.2 Software Trap .................................................................................................................................. 54
15.4.2.1 Programming Example: External Interrupt ................................................................................. 56
15.5 PORT L INTERRUPTS .......................................................................................................................... 56
15.6 INTERRUPT SUMMARY ....................................................................................................................... 56
16.0 WATCHDOG/Clock Monitor ..................................................................................................................... 57
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COP8SBR9LVA8 전자부품, 판매, 대치품
5.0 Connection Diagrams (Continued)
10138942
Top View
TSSOP Package
See NS Package Number MTD56
TABLE 1. Pinouts for All Packages
Port Type
Alt. Fun
L0 I/O MIWU or Low Speed OSC In
L1 I/O MIWU or CKX or Low Speed
OSC Out
L2 I/O MIWU or TDX
L3 I/O MIWU or RDX
L4 I/O MIWU or T2A
L5 I/O MIWU or T2B
L6 I/O MIWU or T3A
L7 I/O MIWU or T3B
G0 I/O INT
G1 I/O WDOUTa
G2 I/O T1B
G3 I/O T1A
G4 I/O SO
G5 I/O SK
G6 I
SI
In System
Emulation
Mode
Input
POUT
Output
Clock
44-Pin LLP
16
17
18
19
20
21
22
23
7
8
9
10
11
12
13
44-Pin
PLCC
11
12
13
14
15
16
17
18
2
3
4
5
6
7
8
48-Pin
TSSOP
11
12
56-Pin
TSSOP
15
16
13 17
14 18
15 19
16 20
17 21
18 22
22
33
44
55
66
77
88
68-Pin
PLCC
22
23
24
25
26
27
28
29
3
4
5
6
11
12
13
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COP8SBR9LVA8

8-Bit CMOS Flash Based Microcontroller with 32k Memory/ Virtual EEPROM and Brownout

National Semiconductor
National Semiconductor

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